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Re: CM40x does not enter deep sleep mode

Hi Mack, IDDINT_DEEPSLEEPis specified as a function of temperature. I am attaching the picture from the datasheet, which will be released soon. So, please refer it as preliminary and subject to change.

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Re: ADE7753 Read register problem

Hi Koseiwind, Could you please try reading a register that has a default value that is not all 0's or 1's, for example the MODE register (Address 0x09) and make sure it returns 0x000C. Looking at the...

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Design Project Looking for an Evaluation Board for DAC

Hello I am a student at university working on a design project and I am trying to find a Evaluation or Demo board for a DAC that can run 14bits and at least 100Msamples.  I was currently looking at the...

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Re: Up/Down Pushbutton Crossfade Control

Thank you so much for the pointers, Bob! Of course I had a missing block in my implementation. Now everything is working correctly! ACW

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New system with ADAU1446 and ADAU1372

Hi All, I am looking for some guidance and confirmation on a proposed new system. I currently have a design that is quite sophisticated in its implementation and requires the utmost in signal fidelity....

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Re: ADR421. Regulator voltage output  is the out of specification under some...

We tested 2 parts (with same date code), they have same behaves. We try to increase the output capacitor in 2 times - this helps. But, we could not understand the root cause of behaves...

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Re: Xilinx Vivado Build Project Files

Please see: https://ez.analog.com/message/172549#172549

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Re: Xilinx Vivado Build Project Files

Moved to FPGA Reference Designs.

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Re: Data clock from AD9361 FMC card in DDR mode

Is LVDS receiver input terminated?

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Sharc Processors and Dolby Atmos and DTS:X

Hi,I have seen the announcement that the current Sharc DSP family will be providing the decoding of the Dolby Atmos signals, and I assume that they will be providing DTS:X capability too. The question...

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Re: AD9364 recieved data verification on windows

Hi Larc ,  Thanks for your reply . I have now done what you suggested. Thanks again . RegardsBhaskar

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Re: SigmaStudio 3.12.1 available?

HI John, Can it be possible to send me the link through i can download SigmaStudio v3.12.1 beta?RegardsAnkur

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ADF4355-2 and ADF5355 Evaluation Board User Guides (Preliminary)

Attached are the user guides for the ADF5355 and ADF4355-2 evaluation boards. It is important to note that these user guides are preliminary versions, and hence are subject to alteration. Update:...

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Re: FMCADC2 - Clock Speed

Hi Pablo, What is the problem you are having? If you want to run the jesd204B lanes slower, you will need to use more lanes,if the system can support it, than fine, otherwise you might have a problem....

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Re: LVDS Clock Jitter?

What hardware are you using? Is it your own design or an ADI evaluation platform?

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AD9364 unable to output Tx Modulated Data

Hello Forum, Using AD9361 Evaluation Software v2.1.4 (64-bit) and the attached AD9364_Project.prj file, I am able to create init script, which contains,1. SPI register programming values.2. The wait...

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Re: Fastest PLL settling time - ADF4351 on FMCOMMS1

1) More information on the ADF4351 cheat sheet: https://ez.analog.com/message/156447. Let me know if you've further questions after that. 2) No. You need to do a band select if you've moved >1 MHz...

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Re: AD9361 out of band IIP3 measurement

Please take a look at this FAQ document. It provides guidelines for measuring in and out of band IIP3.It also provides plots of measured data that you can correlate to. Out-of-Band and In-Band IIP3...

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Re: AD9144 FMC and FMC DAQ2 for ADS7-V1 or other Xilinx FPGA

Some of your questions are best answered by someone from the DAC group.Administrators need to move this question to HS-DAC. 1) The DAC software suite uses a PIC (via an external host) for SPI control....

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Re: ad8317 related

"Small Signal Bandwidth" is the small signal bandwidth of the output amplifier alone.  While the output video bandwidth is essentially the large signal bandwidth of the entire output interface, and...

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