AD5623R Power-on Reset Circuit
Hi,Please give me more information about the power-on reset circuit of AD5623R. 1) What is the start Vdd voltage of power-on reset?2) Must it always be started up from 0 V for the power-on reset? Is...
View ArticleRe: Just a minor question about DDS
Hi Jose Since you wanted to generate these frequencies (150 MHz, 400 MHz, and 1050 MHz) then you need a DDS that has sampling clock speed which is at least X2 of your highest frequency. This leaves...
View ArticleRe: How to add part to the library folder of ADIsimPE simulator?
Hi Jaedong, Thanks for using ADIsimPE in your activity. Here is some useful links on how to import .cir file to the ADIsimPE library. Can Import Pspice models into ADIsimPE?Quick Start user Guide Let...
View ArticleRe: AD9837 Thermal Pad Grounding
Hi D G I'm not an expert in layout but what I could say is to link it to the digital ground, since most of the activities in the DDS are digital in nature. I hope this idea is reasonable. Best...
View ArticleRe: HMC624ALP4E, flatness
I am sorry that I had typos in my last sentence of the previous post. It should be "My system might interpret that the atten. setting is 16.5dB (not 17) instead of 16dB (not 16.5) ?"@
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Re: AD5449 LDAC timing
Hi Robert, Everything looks fine to me. Would you be able to maintain the /LDAC high during the whole sequence just to see how the output behaves? Regards,Mark
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Re: Configurations for KC705 with FMCOMMS1 to run XCOMM example
Hi Dragos, I tried with serial terminal(Putty) set to baud rate 115200 and ran capture.bat but there was no activity at the Serial terminal. There was an error message as shown below: (Ran the bat...
View ArticleRe: ADV7614 Dolby/DTS TrueHD audio support.
Have you licensed our software driver source code for ADV7614? -Matt
View ArticleRe: HSC-ADC-EVALEZ+AD9656 Matlab control
Hi Said, I'm sorry for the delay. I sent an email to your registered email address. Please let me know if you don't get it. Thanks,Michael
View ArticleRe: Drivers to Communicate [ AD9269 + HSC-ADC-EVALCZ ] with third party...
Hi Touseef, As long as you're using the FPGA file distributed with VisualAnalog and using the Example_AD9640.m as a starting point, it should be possible to get both channels. You'll need to modify...
View ArticleRe: AD9129 reference design for Altera
Did you ever get a response to this? I've been looking into the same thing...
View ArticleADS simulation libraries for HMC524LC3B, HMC499LC4, HMC1040LP3CE
Hi All, This is Wasim here. For some research activity I want to use HMC524LC3B, HMC499LC4, HMC1040LP3CE. However before building the hardware I want to simulate it into Agilent Advanced...
View ArticleADuCM706x:Download firmware via RS485?
Dear Sir, I use ADuC7061 for sensor module, it works now. however, I would like to know if it is possible to download firmware via RS485?since RS485 is half depulex communication, an autodirection...
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Re: Cannot get ADV7180 to display video through ADV7513
I have good news! Using much of the code Rob.Analog code, I was able to get some information to begin leaking out of the ADV7513. I connected our design to a Signal Generator and was about to capture...
View ArticleRe: sigmastudio 3.11.1 support for adau1372
Hello David, Thank you for the clarification! Bob
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Re: AD9656EBZ inputs sychronisation problem?
Hi Said, I've attached a guide for using the external trigger feature of the HSC-ADC-EVALEZ. With the existing FPGA code, there will be a time uncertainty of about 100ns with respect to the external...
View ArticleLabview source vi's for AD7173-8 eval
We're looking to take our evaluation to the next step. The eval pc software is a compiled version of a Labview gui.A link or attachment to the Labview sources would be appreciated. Thanks. knap
View ArticleRe: Design with AD8338
Hi,I am glad to help. If you have any questions on your future applications involving ADI products don't hesitate to post it here. Someone from this community will be eager to help you.By the way, may...
View ArticleRe: Using axi_ad9361_dev_if in LVDS FDD Mode
OK. Thanks. Regarding A1, it is still not clear how it is working. I assumed that my FPGA drives tx_data on the rising edge of fb_clk(fb_clk_p) and the device was capturing the data on the falling...
View ArticleRe: Can I run 2 ADAU1701 in parallel completely independent of each other ?
Thanks Dave T for teaching me this!
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