Hi Touseef,
As long as you're using the FPGA file distributed with VisualAnalog and using the Example_AD9640.m as a starting point, it should be possible to get both channels. You'll need to modify ReadFIFO.m to fill the FIFOs once, then read back data and interleave both channels in the FPGA. I think the maximum number samples you can capture from each channel is 32K in this mode. Please note that the channel numbers are swapped...channel A is 2 and channel B is 1.
Regards,
Michael