Hi Jose
Since you wanted to generate these frequencies (150 MHz, 400 MHz, and 1050 MHz) then you need a DDS that has sampling clock speed which is at least X2 of your highest frequency. This leaves me an option to recommend to you AD9915 which has a clock freq of 2.5 GHz. In the case of using the PLL internal to the chip, you needed a multiplier of x100 given the clock frequency that you specified. Please refer to the AD9915 datasheet page 21 for more details in using the PLL.
I just want to clarify that the clock frequency after passing through the PLL (if not bypassed) would be the system clock frequency. This frequency is being used by the DAC, thus this specifies a limit that the clock frequency should be X2 of the highest output frequency. I also want to add that you need to add an LPF filter that has a cut-off frequency approximately equal to the nyquist frequency.
Best Regards
Louijie