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Re: AD9364 Tx Output Power

Are you using the Linux or no-os drivers?

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ADF4350/1 & ADCLK846

Hi I need to clock several AD9613 ADCs simultaneously, with a configurable clock. I've thought about using an oscillator to as input the ADF4350/1 PLL to generate the clock, then distribute it to all...

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Re: ad9361

Have you checked out the on line documentation? http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz It details the simulation solution (based on MathWotks SimRF), and the Linux drivers,...

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Re: Evaluation board EVAL-ADV7612-7511P

The scripts only handle configuring the devices in a static mode for various formats.  EDID and HDCP handling is a dynamic process which the embedded 'repeater' code handles.  To get the 'repeater' you...

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AD7856 Calibration mode and test mode

Hi ,     My customer is using AD7856 now, They don't know when they should use Calibration mode and test mode, And there are no more detailed description  about test register and calibration...

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Re: AD7794 Evaluation Kit LabVIEW Source Code?

Dear Chris,I'd be interested to the Labview source code and/or libraries to make the eval board work in my Labview program.May You send me any information/material/link?Many thanks in advance!David

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Re: ADV7182 switches standard when no input

We strongly suggest that customers start their evaluation with one of our evaluation boards. Are you using the scripts for our ADV7182 evaluation board?ADV7182 Design Support Files -Matt

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Re: AD-FMCOMMS1-EBZ Evaluation Software and VHDL code

Thank you very much. In the first link there is a pre-build image for the devices. Is available the source code anywhere? I would be interested in the vc707_fmcadc2_2014_R2_PRE.zip source code.Thanks...

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Re: AD9139, DAC latency from input to output

That's fine. I do not mind explaining this.First of all we can guarantee Reg[0x05].bit5 will be set after one single sync.As for the figure 39 in the datasheet, it's my idea to do that. Why?<1>...

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Re: AD-FMCOMMS1-EBZ Evaluation Software and VHDL code

All the sources are on GitHub: Analog Devices Inc. · GitHub You may want to start from here: AD-FMCADC2-EBZ FMC Board [Analog Devices Wiki]

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Re: Vivado 2014.2 possible bug

Thanks for letting us know. However we don't really do any of these workshops nor are we familiar with the project that gave you this error. If you are looking for an answer/solution- it is best to...

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LabVIEW Interfacing with AD9914 Eval Board

Hey All,I am looking to communicate with an AD9914 eval board through LabVIEW.  I’ve checked out old engineerzone posts and nothing seems to be recent or giving me the help I need.  I was wondering if...

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Re: AD-FMCOMMS1-EBZ Evaluation Software and VHDL code

Thank you very much for the information!One last question,Is the code in this address: hdl/system_top.v at master · analogdevicesinc/hdl · GitHub the source code of the builded pre-image...

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low cost hart sensors (AD5700)

hi, I am using an AD5700 as HART modem on my board. For demo purpose, I am looking for low cost light HART sensors . Have you some manufacturers to propose ? Thanks,

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Re: AD-FMCOMMS1-EBZ Evaluation Software and VHDL code

Almost - https://github.com/analogdevicesinc/hdl/tree/hdl_2014_r2/projects/fmcadc2/vc707 The prebuild uses the 2014_R2 branch. -Michael

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Re: Direct Digital Synthesis Start-Up

Hi Arslan, If you don't mind me asking, how did you get communication to work?  I've heard from most customers in the past that most USB to parallel port adapters do not work.  I created a powerpoint...

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Re: How to configure display timing via EDID

Looking at the attached file it looks like you already set it up both in the VESA->DB1 block and the CEA->DTDs block. Is the source reading and accepting the new timing parameters.  What is the...

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AD9910 Eval board software

Hi, I've just got my hands on an AD9910 Eval board and I am using the software to control it from a computer. Although my question is quite trivial, I just want to clarify why the GUI of the software...

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BOM for the AD9625 Eval board and Eval board question

Hello,   When you go on the Analog Devices website under AD9625 and click on ‘Evaluation Boards & Kits’ then click on ‘AD9625 Evaluation Board Documentation (Wiki Site)’ then click on ‘BOM’ you end...

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Re: AD9361 LVDS DATA_CLK

It is possible that signal integrity is being impacted by layout, stubs and your measurement setup. Do you have the line terminated on the FPGA end? You could perhaps select another LVDS pair to probe...

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