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Re: AD9139, DAC latency from input to output

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That's fine. I do not mind explaining this.

First of all we can guarantee Reg[0x05].bit5 will be set after one single sync.

As for the figure 39 in the datasheet, it's my idea to do that. Why?

<1> After the first effective Frame, it will take some time to get Reg[0x05].bit5 set for the sync logic. So the loopback means wait until lock status is set. I do not want the user do anything before sync lock is asserted.

<2> In addition, I think it's a always a good way to avoid any unknown potential cause to make sync lock fail if we double check the lock status after we initialize sync.

 

Any concern from customers, please let me know. I would like to explain.

 

Jerry



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