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Re: Obtaining the desired rx_clk_in in the FPGA

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Hi Istvan,

 

thank you for your reply. If you read the last paragraph of our original question you will see that indeed, we have unsuccessfully tried to modify the FIR interpolation rate. Independently of the interpolation factor required by the digital-filtering configuration file (i.e., both generated with the wizard and manually modified), the FIR factor is shown to be x2 (i.e., both from the GUI and through command line). It seems as if not all possible FIR/HB configurations are supported when targeting a 1.4 MHz BW.

 

Oriol


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