Re: Obtaining the desired rx_clk_in in the FPGA

Hi Oriol,

The reason of the 4x times relation is quite simple, on 2rx2tx mode, you going to have two ADCs and two DACs, that means your LVDS interface needs to run 4 times faster to be able to move the required amount of data on both transmitter and receiver side.

But you can change the interpolation factor of the filter, in case of FIR you can choose 1x, 2x, or 4x. Did you try that?

Istvan