Hi Zach,
When DSB tested the synchronizing two eval boards, he didn't cut any traces he just overdrove the pin using a pattern generator. In CN-0121 it shows a DG2020A driving the I/O_Update lines. In Keith's response above he did cut the I/O_Update trace at or near the FPGA, but left a trace between the I/O_Update and header U6 intact so he could use U6 to control it.
If you are trying synchronizing multiple boards and use the PC software to control boards, I don't think you can use the internal I/O_updates and keep the two boards synchronized. When the software sends new register writes to the AD9910, the SPI communication is done asynchronously to the boards, so you don't know when your register writes are happening relative to the SYNC_CLK and the internal I/O_Update. You can try it, but you'll likely need to send manual updates to both boards that way you can guarantee your updates are occurring after the register writes.