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JESD204 Interface Framework - Eye scan

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Hello,

I have successfully applied JESD204 Interface Framework on my board with ad9695 ADC. I have ADI IIO Oscilloscope up and running. For linux I am using Analog devices brqanch master-4.14. 

physical and link layer drivers:

axi_adxcvr - adi,axi-adxcvr-1.0

axi_jesd204_rx - adi,axi-jesd204-rx-1.0

And my question is how can I perform eyescan? It seems that axi_adxcvr hdl component has eye scan capability, but corresponding linux driver does not has support for it. I noticed that adi,axi-jesd-gt-1.0 driver has eye-scan capability but is otherwise not compatible with di,axi-jesd204-rx-1.0.

What drivers and configuration should I setup to perform eyescan?

Relevant DTS:


axi_adxcvr_0: axi_adxcvr@80000000 {
compatible = "adi,axi-adxcvr-1.0";
//compatible = "adi,axi-jesd-gt-1.0";

reg = <0x0 0x80000000 0x0 0x10000>;
clocks = <&clk0_adc_clk>, <&clk0_adc_ref_clk>;
clock-names = "conv", "div40";
#clock-cells = <1>;
clock-output-names = "adc_gt_clk", "rx_out_clk";
adi,sys-clk-select = <3>;
adi,out-clk-select = <4>;
adi,use-lpm-enable;
};

axi_jesd204_rx_0: axi_jesd204_rx@80010000 {
compatible = "adi,axi-jesd204-rx-1.0";
interrupt-names = "irq";
interrupt-parent = <&gic>;
interrupts = <0 89 4>;
reg = <0x0 0x80010000 0x0 0x10000>;
clock-names = "s_axi_aclk", "device_clk", "lane_clk";
clocks = <&clk 71>, <&axi_adxcvr_0 1>, <&axi_adxcvr_0 0>;
adi,octets-per-frame = <1>;
adi,frames-per-multiframe = <32>;
#clock-cells = <0>;
clock-output-names = "jesd_adc_lane_clk";
};

Link status:

# cat /sys/devices/platform/amba_pl/80010000.axi_jesd204_rx/lane0_info
CGS state: DATA
Initial Frame Synchronization: Yes
Lane Latency: 2 Multi-frames and 23 Octets
Initial Lane Alignment Sequence: Yes
DID: 0, BID: 1, LID: 0, L: 3, SCR: 1, F: 0
K: 31, M: 1, N: 15, CS: 0, N': 15, S: 0, HD: 1
FCHK: 0x62, CF: 0
ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 0
FC: 6000000
# cat /sys/devices/platform/amba_pl/80010000.axi_jesd204_rx/lane1_info
CGS state: DATA
Initial Frame Synchronization: Yes
Lane Latency: 2 Multi-frames and 25 Octets
Initial Lane Alignment Sequence: Yes
DID: 0, BID: 1, LID: 1, L: 3, SCR: 1, F: 0
K: 31, M: 1, N: 15, CS: 0, N': 15, S: 0, HD: 1
FCHK: 0x63, CF: 0
ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 0
FC: 6000000
# cat /sys/devices/platform/amba_pl/80010000.axi_jesd204_rx/lane2_info
CGS state: DATA
Initial Frame Synchronization: Yes
Lane Latency: 2 Multi-frames and 26 Octets
Initial Lane Alignment Sequence: Yes
DID: 0, BID: 1, LID: 2, L: 3, SCR: 1, F: 0
K: 31, M: 1, N: 15, CS: 0, N': 15, S: 0, HD: 1
FCHK: 0x64, CF: 0
ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 0
FC: 6000000
# cat /sys/devices/platform/amba_pl/80010000.axi_jesd204_rx/lane3_info
CGS state: DATA
Initial Frame Synchronization: Yes
Lane Latency: 2 Multi-frames and 25 Octets
Initial Lane Alignment Sequence: Yes
DID: 0, BID: 1, LID: 3, L: 3, SCR: 1, F: 0
K: 31, M: 1, N: 15, CS: 0, N': 15, S: 0, HD: 1
FCHK: 0x65, CF: 0
ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 0
FC: 6000000
# cat /sys/devices/platform/amba_pl/80010000.axi_jesd204_rx/status
Link is enabled
Measured Link Clock: 149.780 MHz
Reported Link Clock: 150.000 MHz
Lane rate: 6000.000 MHz
Lane rate / 40: 150.000 MHz
Link status: DATA
SYSREF captured: Yes
SYSREF alignment error: No


Re: FDD independent mode

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Along with moving ENSM to FDD you need to enable FDD External Control Enable bit 0x15[D7].

 

I think you are using below parameter 

1, //frequency_division_duplex_independent_mode_enable  

is so then 0x15[D7] bit will be set and still it is in FDD independent mode. 

 

Try disabling it 

0, //frequency_division_duplex_independent_mode_enable 

Re: FDD independent mode

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In FDD it is working properly, but i want in FDD independent mode where i can control my tx and rx using pins, In FDD i can't control both tx and rx independently.

Re: FDD independent mode

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I think we started deviating from the actual problem. let me explain u my scenario, i want to work in FDD independent mode using pin control method. In observation we found Txon is 0 when we configure 0x035 register with value 9 ,so please go through that register 0x035 and let me know what to do to make Txon is 1 so that my problem get solve

AD9467 Readback problem

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Hi,

we are using AD9467 in our design. I am trying to readback chipid just to verify the spi interface. To readback reg 0x01 I am sending the x"8001" data over sdio line. Expected data 0x50 should be seen on sdio line the next eight clk cycles, but I am unable to see the data . 0x00 is seen. Can you please help me what could have been the issue. Do we need to do anything else for readback.

I have captured sclk and sdio at ADC input . Plz find attached the image of the same.

 

Thanks and Regards,

sumala

ltc3807

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Hello,

I planned to use the LTC3807 in order to make a power supply with a current between 20A and 25A.

 

I saw a current limit at 25A in the product list on the website and a limit of 20A in the LTC power CAD software.

My questions are :

- What is the current limit for this component?

- What is the reason of this limit, all switching components are externals so could you explain me why there is a current limitation (Duty cycle, gate driver,...)

 

Thanks

Matthieu Baque

Re: Pass element LT1764A and LT1963A

AD9172 custom design mismatching jesd204 parameters

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Hi,

 

I'm currently developing a project based on the AD9172. For that purpose, I bought one eval board and the ADS7v2.

They work correctly together and now I want to use another FPGA board (the ZCU102), so I designed a simple FPGA project based on the JESD204 IP from Xilinx.

 

I want to use JESD204 mode 2 (3 lanes). I configured the IP like this (IP core shared in design):

I program the FPGA and then I set the DAC with ACE like this:

I must change some registers because my clocking scheme is the following:

For the AD9172:

Registers

Value

Comments

0x308

0x8

physical lane 0 correspond to logical lane 0, phy 1 to log 1 etc.

0x309

0x10

0x95

0x0

Enable PLL

0x790

0

Required

0x791

0

Required

0x796

0xE5

Required

0x7A0

0xBC

Required

0x794

0x08

Recommended CP current

0x797

0x10

Required

0x797

0x20

Required

0x798

0x10

Required

0x7A2

0x7F

Required

Pause 100 ms

0x799

0xC3

Output clk = dac clock /4, N div=3

0x793

0x18

Input divider = 1

0x94

0x00

DAC clock = VCO / 1

0x792

0x2

Reset VCO

0x792

0

Pause 100 ms

0x7B5

READ

If locked, equals 1

For the HMC7044:

Registers

Value

Comments

3

0x2C

Disable PLLs

5

0x6F

CLKIN1 as external VCO input

0x64

0x1

External VCO

0xED

0

CLKOUT3 output mux = channel divider

0x151

0

CLKOUT13 output mux = channel divider

0x14B

0x40

CLKOUT13 divided by 64 -> 500 / 64 = 7.8125 = sysref to FPGA

0x14C

0

0xE7

0x40

CLKOUT3 divided by 64 -> 500 / 64 = 7.8125 = sysref to DAC

0xE8

0

0xE3

0

CLKOUT2 output mux = channel divider

0x147

0

CLKOUT12 output mux = channel divider

0xDE

0

CLKOUT2 divided by 2 -> 500 / 2 = 250 = data rate clock unused because external dac clock

0xDD

0x2

0x142

0

CLKOUT12 divided by 2 -> 500 / 2 = 250 = data rate clock to FPGA

0x141

0x2


Re: AD9172 custom design mismatching jesd204 parameters

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Sorry, I just click on 'post'.

 

So after all these steps, I verify that the SYSREF and data rate clock are correctly seen by the FPGA; they are.

Furthermore, the DAC PLL, the JESD PLL and the DAC DLL are locked.

The link is established : frame sync, code group sync and ILAS are OK:

However, Good Checksum is never lit.

I checked register 0x400 to 40D, they don't correspond to the register 0x450 to 0x45D. It means that received link parameters during the ILAS doesn't match the DAC configuration. (As mentionned on page 49 of AD9172 datasheet).

 

I keep searching but I cannot find out why.

Could someone help me?

 

Thanks in advance

AD9363: calculate RMS power from RX I and Q samples

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My software captures some I and Q samples from RX ports via LVDS interface, I need to calculate the average RMS power of the samples. To calculate the voltage of the sample, I would use the below formula

 

Vsample = sample_code * Vreference / ((2^Nbit - 1) * root_square(2))

where Nbit is 11, is it right?

what is the value of Vreference for the AD9363?

 

Thanks and Regards,

Ramon

Re: Crosstalk about AD9653

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And I cut off the connection between pre-stage AMP and AD9653, I get pic4 (input of AD9653).
Does it mean there is something wrong with my layout or it is a common phenomenon ?

 

pic4:

pic4

AD2S1210 velocity 0 Resolver position

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Hello

 

I have questions when the resolving velocity of the resolver is 0.
· Can AD2S1210  detect the position after startup or reset
· We use two resolvers for switching. Is it possible to detect when the resolver on the switched side is stationary?

 

Thank you.

ADF4350 RF Application

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Project functional requirements:

RF data transmission,Communication distance farther than 1km,frequency hopping

ADF4350 whether it can do that,Or a matching chip scheme?Or other recommendations?thanks!

The VCXO_VT output of the AD9528

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Hello! 

when I use the AD9528, when the PLL1 is locked,the vcxo_vt output 1.8V,  I test the AD9371 Evaluation board ,the vcxo_vt output 2.5V. Is my board  instable? How can I modify my board.

Re: ERROR(ORPSIM-15108): Subcircuit AD8232 used by X_U1 is undefined

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Hi,

This is my test schematic.

Thanks 


Re: (ADR35xx)Datasheet change Rev.0 to Rev.A

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Hi 

 

Thank you for your reply.

 

So is it OK to understand that ADI changed "unit" only for P11,12,14?

 

Best regards

Kawa

Re: EXTCLK application for AD7768-1

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Hi Niall,

 

Thank you very much.

 

B.Regards,

Linear

Re: How to match LTC5562 LO ranging from 3GHz to 7.5GHz

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Table 2 shows single ended LO input impedance and reflection coefficients which are not consistent with each other. For example, at 10MHz, impedance is 195.29-j2576.34 but magnitude of reflection coefficient is shown as 0.59 (it should be 0.997 for this impedance at 50 ohms).

Also, using a simulator to plot return loss given the table 2 impedances and table 4 matching components differs significantly from the curves shown in Figure 8.

Re: AD8302 overheating

Re: ERROR(ORPSIM-15108): Subcircuit AD8232 used by X_U1 is undefined

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Hi,

This is my test schematic. I think the problem may be that naming characters of the pins are too long, but I dare not modify the source files from the official website. I hope you can help me   solve this problem.

Thanks

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