LT8390 chokes while driving motors in Buck mode

July 9, 2018, 9:42 am

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Hi

 

I developed a schematic for a synchronous buck converter based on  LT8390 reference design.

I am stepping down a voltage of approx 40V (From a LiPo battery) to 24Volts.

 

However if i increase motor RPM even in a moderate way, the motor stalls for lack of current and output voltage drops significantly.

 

If the motors are powered directly by a 40V or 24V battery, there is no problem at all. I can increase or decrease RPM as fast as humanly possible and the motors never stall.

What am i doing wrong ?

Attached is the schematic that i am using..

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Re: AD9361 TDD Isolation/Leakage Concern

July 9, 2018, 9:50 am

≫ Next: Re: DDS AD9910，used for Radar signal processing, found the amplitude of the linear-frequency-modulation signal output changes regularly, like a sine wave

≪ Previous: LT8390 chokes while driving motors in Buck mode

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Got it -  another question then, is there any significant benefit then in using TDD mode vs FDD mode with an RF TX/RX switch ? From what I understand, with the TDD mode we have delays like ADC turn on, VCO calibration, etc while in FDD mode we would avoid these. The downside for FDD would be the increased power consumption of keeping both tx/rx chains fully running despite only 1 is being utilized at a time. Is there any quantification of the delta in power consumption between the two approaches?

Re: DDS AD9910，used for Radar signal processing, found the amplitude of the linear-frequency-modulation signal output changes regularly, like a sine wave

July 9, 2018, 11:48 am

≫ Next: AD9837 setup problem

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Be aware that in the time domain an LFM signal will not necessarily contain samples at the peak points of the average sinusoid. Attached is a plot of a 500ns chirp from a simulation using the parameters in your post (f_start=88MHz, f_stop=152MHz, f_step=160kHz, t_step=5ns). Note the samples generated by the DDS do not always coincide with the normalized peak of the sinusoidal waveform. This is expected behavior for a digitized LFM signal.

 

Could this be the cause of the amplitude variation you are seeing?

AD9837 setup problem

July 5, 2018, 3:17 pm

≫ Next: Re: Problems with ADXL372 self-tests ?

≪ Previous: Re: DDS AD9910，used for Radar signal processing, found the amplitude of the linear-frequency-modulation signal output changes regularly, like a sine wave

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Hello all engineers,

 

I'm currently testing AD9837 evaluation board in conjunction with an evaluation board C8051F340 from Silabs. I've looked around and read the AD application not AN-1070 to find the solution to my problem but still struggle with it so, I'm asking you all here if you can help shed some light on my problem.

Here is what I understand about the write sequence to the AD9837 device:

• Send 0x2100 (Reset device and set bit D13 to 1)
• Send 0x1234 (write to LSB frequency register 0)
• Send 0x5678 (write to MSB frequency register 0)
• Send 0x4321 (write to LSB frequency register 1)
• Send 0x8765 (write to MSB frequency register 1)
• Send 0xC000 (write to phase 0 register)
• Send 0xE000 (write to phase 1 register)
• Send 0x2000 (Exit reset)

Ok, my question here is every time I need to send a 16 bit command to the AD9837 device, I have to send 2 bytes (8-bit for each write). However, which byte I need to send first? Lower byte or the higher byte need to be sent first? 

I've tried but didn't have any lucks with both ways. The device don't seem to behave the way it should.

Please assist if you can, any help/inputs would be greatly appreciated. Thanks and have a wonderful day.

 

Best Regards,

TLN

 

PS: The attached file is the code to config the device. Please take a look if you can and tell me where I did wrong. Thanks

Re: Problems with ADXL372 self-tests ?

July 9, 2018, 1:10 pm

≫ Next: Re: How to set up stable JESD204B links between Multi-AD9154

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I have performed the "1000x test" on the same part.

 

The accelerometer is located inside my system and each time my system is powered-ON the self-test is performed. If my system detects failure on the accelerometer it goes in "Error Mode" as it's a critical component of the system.

 

The test I've done reboots continuously my system and verify that it's not entering the "Error Mode". If I restart the system after an accelerometer failure the self-test pass again.

Re: How to set up stable JESD204B links between Multi-AD9154

July 9, 2018, 1:24 pm

≫ Next: Re: ADXL327 Bias Voltage

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Hi allendia,

 

I would agree - my guess would be that the amount of jitter on the generated SYSREF may be too large, over time, stepping the edge outside the programmed Delay and Variable margins (typically denoted as DEL and VAR) on one or all the AD9154 in the system. Or, alternatively, the jitter on the Fdac clock (since used to generate the LMFC for each DAC) is too excessive, in which case it is a function of your PCB layout in terms of how these "jitters" compare relative to one another, and SYSREF, over time and possibly over temperature.

 

Consider trying to slow the SYSREF clockrate down to check when the link becomes unstable. It would hint at the amount of "jitter margin" your DACs have, and which is the worse. Increase VAR and make sure your DEL is accurate to place it at the window center.

 

To note, the HMC7044 has 1/2 the jitter the LMK04828 does. Although you could likely fix the problem by properly setting up the AD9154s according to your system clocking requirements, and still use the TI part

 

I hope this helps.

 

Best Regards,

Arik

Re: ADXL327 Bias Voltage

July 9, 2018, 1:45 pm

≫ Next: Re: LTC3119 EMI tests

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1.63V does seem to be within the range of offset that is offered in the datasheet.  Unfortunately, I haven't been able to find any data for the drift that would be expected from these units. What type of stability do you require?

Re: LTC3119 EMI tests

July 9, 2018, 1:51 pm

≫ Next: Re: Multiple AD9154 chips synchronization by using ads7-v2

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Hi, we do not have any EMI test results on LTC3119 at present.

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Re: Multiple AD9154 chips synchronization by using ads7-v2

July 9, 2018, 1:58 pm

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Hi Chong,

 

An old issue I suppose, so for the sake of completeness: you would need to clock both DACs from a single clock source, bypassing the EVB onboard clock, which would make sure all clocks are aligned. Then set the AD9154's and the ADS7's into JESD204B subclass1, to align both links to a single SYSREF reference (typically referenced to- or generated from- the DAC clock).

 

Best Regards,

Arik

Re: Problems with ADXL372 self-tests ?

July 9, 2018, 2:09 pm

≫ Next: Analyzing the ADSP 21469 anomalies

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I see what you mean. For a single part, recently we've seen similar issues happen under 2V and we're in the process of improving our screen method to filter these parts out originally. But as for now, the only way we can provide at sensor level is to increase the Vsupply above 2V supply or conduct calibration to check offset and sensitivity.

Analyzing the ADSP 21469 anomalies

July 9, 2018, 2:21 pm

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Hello,

 

I am trying to understand the anomaly provided by AD on ADSP-21469 and during the course came across couple of questions/clarifications.

 

Visual DSP ++ 5.0 Update 8 used to compile and load program into target. ADSP-21469 Silicon Revision 0.2 used in program and while going through the anomalies many were mentioned about ( please consult the "Silicon Anomaly Tools Support" help page in the applicable documentation and release notes for details.). Not sure what that means...

 

For example refer to adsp-21467_21469-sharc-anomaly.pdf 

15000002 anomaly workaround section.

 

Having tough time to understand some of the anomalies listed in the document. 

 

Our project configuration is as follows:

All of the processor specific library functions configured in 48-bit space and in internal memory.

Application code configured as 16-bit VISA and stored in internal momery

Complete data memory configured in external DDRAM as 32-bit.

 

with the above information, is there a way to figure out which anomalies applicable and which are not?

 

Any comments or feedback on this highly helpful

 

Thanks

Ram

AD9695 question

July 9, 2018, 2:31 pm

≫ Next: Re: ADXL327 Bias Voltage

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I want to use ADS7-V2EBZ as data capture for board level test and also Xilinx Development Tool for JESD204B interface between AD9695-625 ADC chip and Xilinx FPGA.

If we purchase the ASD7-V2EBZ, can we get the source Verilog code of Xilinx chip?

Re: ADXL327 Bias Voltage

July 9, 2018, 3:18 pm

≫ Next: How to match LTC5562 LO ranging from 3GHz to 7.5GHz

≪ Previous: AD9695 question

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Thanks NevadaMark.

If the bias output stable at room temperature, the calibration will work. otherwise, calibration won't work.

How to match LTC5562 LO ranging from 3GHz to 7.5GHz

July 9, 2018, 3:29 pm

≫ Next: Envelope detector or IQ Demodulator for the receiver for a FMCW Radar

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How do I match LO port of LTC5562, my LO ranges from 3GHz to 7.5GHz?

Envelope detector or IQ Demodulator for the receiver for a FMCW Radar

July 9, 2018, 3:39 pm

≫ Next: Re: Crosstalk about AD9653

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I'm going to design a FMCW radar for a project and was wondering which one is better to use to detect the receiving signal.

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Re: Crosstalk about AD9653

July 9, 2018, 3:54 pm

≫ Next: LTC3621 absolute max Vin is 17V?

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Hi Chen,

 

Thanks for using the AD9653 in your system.

 

• You said that "The second picture is the input of AD9653 when AD9653 is not working." When you say "not working", does that mean that the AD9653 is powered down?
• The AD9653 has switched capacitor inputs. As such there will be a lot of switching artifacts at the ADC inputs. In the time domain these occur between sampling instants, so they do not cause a problem. In the frequency domain I'm not sure how they will appear, but there will certainly be additional tones compared to when the ADC is powered down.
• You mention that you suspect the signals are coming from the pre-stage analog circuit. Are the frequency components you see in the third picture what are present in the pre-stage?
• Have you confirmed that the AD9653 outputs are being captured correctly? The AD9653 has output digital test patterns in case that would help.
• To be sure the AD9653 is in the proper operating state, would you please do a Digital Reset on AD9653 after your system is powered up and in steady state?
  • Write Register 0x08 = 0x03
  • Write Register 0x08 = 0x00

Thanks,

 

Doug

LTC3621 absolute max Vin is 17V?

July 9, 2018, 4:22 pm

≫ Next: Re: How to handle the twelve bit location data of AD2S1210？

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In operation description, it talks about overvoltage protection that engages at 19V.  What is the real max Vin?

Re: How to handle the twelve bit location data of AD2S1210？

July 9, 2018, 5:26 pm

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and the received data of my position register is 11bit long，  not 12bit

 the most significant bit of the position register is always zero

Re: digital ramp and phase clear in AD9914

July 9, 2018, 6:07 pm

≫ Next: VDD_DMC power supply without DDR memory

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I seem to have ambiguously spoken. The same signal is input to the DRCTL pin and the OSK pin. (For example, if the pulse length is 1us and the period is 10us, the signal type to the DRCTL pin and OSK pin is high for 1us and low for 9us.) CFR1 [9] and CFR1 [8] are set to one. Even if CFR2 [15] = 1, there is no difference.

The previous questions are:

  1. Why does such a large delay occur?

  2. How many sys_clk (3.5 GHz / 24) does the delay have?

  3. Is there a good way to match the timing of the OSK and LFM signals internally?

 

Thank you for always responding to my question.

VDD_DMC power supply without DDR memory

July 9, 2018, 6:41 pm

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Hello

 

I saw the question "Use ADSP - 21584 without DDR".

 

In the case of other ADSP-2157x as well,
if external DDR memory is not used, can the VDD_DMC power supply be unconnected?

 

Best Regards