Mr. Guenter
Thanks again for your answers on this. I didn't mean to discuss about what resistor divider network will get what gain level of the input signal. I post our schematic design here. The voltage level of the differential CVBS signal we measured at the input port Ain 1,2 here is about 0.5Vp-p
My only question is that, if this 0.5V level is ok for the chip's ADC to work properly?
You know for NTSC, it measures luma or chroma by IRE. But for PAL, the luma and chroma are measured by its voltage level. For a standard CVBS signal, the Vpp is 1V and here the input CVBS signal to the chip in our design is 0.5V, we are just curious about if it can work properly.
Thanks,