Hi Mikael,
Yes. For AD9851, you can issue frequency update (FQ_UD) to transfer data from buffer register to active register. Looking at the timing characteristics, the latency defines how many clock cycles before frequency or phase output changes. So, a sinusoidal signal is expected at the output after 18 SYSCLK cycles. So if you have a SYCLK of 180MHz, period would be 5.56ns, you can then compute the number of periods to produce a signal.
Hope this helps,
Sitti