Re: Data clock from AD9361 FMC card in DDR mode

Tomas:

If the spec on page 6 of the dataseet (DIGITAL DATA TIMING (CMOS), VDD_INTERFACE = 1.8 V / Capacitive Load) is max (like you state) - it should be over a column.

What is in the datasheet is typical, with no min, no max.

-Robin