Hi Rejeesh,
Thanks for the updated wiki. I do have a question about multiple cores in the master/slave scenario.
I am using two AD9361 external devices connecting to two axi_ad9361 cores in a Zynq. I was planning on slaving both cores to the RX_CLK_IN clock input received from the external AD9361. This would result in the two cores being asynchronous to each other with no master/slave relationship. Is there any weakness in my approach that is overcome by using the two cores in a master/slave scenario?
On another note, I found another I/O port that is not explained in the wiki and that is the input port named "delay_clk". From the source code, it appears that the delay clock frequency must be 200MHz. Does the AXI-lite ACLK need to be the same clock so that the delay status synchronous to delay_clk can be read by the AXI-lite interface? Or can the the delay clock be completely asynchronous to the AXI clock?
Thanks for your help!
John