Quantcast
Channel: EngineerZone: Message List
Viewing all articles
Browse latest Browse all 22625

Re: ADCLK custom board design

$
0
0

Thanks for reply DSB, I've been away so couldn't see earlier.

 

So I made my own custom board keeping all the trace lengths as short and equal as possible (lengths of CLK, CLK_BAR, 0, 0_BAR, 1, 1_BAR).

Here are some details of my setup:

 

i) Vs= 1.8V

ii) CLK_frequency: 100 Mhz/16= 6.25 (100 MHZ to DDS AD9910, which then outputs a 6.25 MHZ LVDS signal)

iii) CTRL_A, CTRL_B and SLEEP are permanently tied to ground (directly, seeing as they are already internally pulled down)

iv) EPAD=GND

v) Only using output 0 and 1.

 

 

Something like how ADCLK 846 is connected in this discussion but with CLK and CLK_BAR as LVDS instead of CMOS:

https://ez.analog.com/thread/49749

 

My problem:

 

I directly connect SYNC_OUT+ and SYNC_OUT- from AD9910 to my ADCLK846 board. First I tried with the DC coupling (capacitors in clock path removed). Nothing happened. Then I tried with bypass capacitors in place and lastly i tried biasing with VREF (as shown in ADCLK846 Eval board schematic), and still nothing. Am I missing something? Do I have to take care of input resistance of clock buffer ic?

 

Kindly provide some reference design for LVDS buffer if possible.

 

thnx.


Viewing all articles
Browse latest Browse all 22625

Trending Articles



<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>