Hi David,
Please have a look at the snapshot collected with ChipScope:
this shows the ADC-Signals after the input interface. All data is now parallel (DDR from ADC), and we see the test pattern (D0-D5 = all ones, D6 - D11 all zeros) is stable. Therefore I adjusted the delays in the FPGA between 18 and 20 taps. All seems ok.
In this snapshot, the ADC is in normal mode with no input signal. You see that the digital data shows values between -1 and +1 which would be as expected. But, there are also these +63, -64 values. I would have expected that all bits toggle in the same manner but they don't. The lines D6-D11 seem to be delayed but how can I shift them back without shifting D0-D5?
Thank you very much for your help, David.
Kind regards,
Dino