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Re: "High-Speed" ADC used for single-pulse conversion

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Hi,

Even our pipeline ADCs have a S/H function at the front end to sample the input (I think this equates to your "freeze" term), and they are triggered by a differential sample clock input.  These inputs are typically not specified as  being logic family compatible, but a differential PECL signal is often used.  If 10 bits of resolution would be sufficient, then I would recommend looking at the AD9608. 

www.analog.com/AD9608

 

Regards,

David


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