Jetmir,
"it is not a good idea to ad new IPs at reference design since it will change the registers space for the software part. " - this statement is only true, if you're IP has internal registers, which can be accessed by an AXI slave interface. Without any internal registers, the software won't see the IP. This is not necessarily an issue, if you don't want to change the functionality of your IP from software.
A1: You said that your IP worked on simulation, so it should work on hdl too, if the integration is done properly. If you want to integrate it into the data path, make sure you have adapted your IP to our FIFO interfaces. What's the state of the valid and enable signals? What about the overflow and underflow?
A2: If you're IP does not have any internal register, the right connection in the hdl should be enough.
I do not really recommend to integrate you IP into the axi_ad9122, I think it's more feasible to put it between the DMA and the core. You just need to make sure that all the data width and control signals are matched.
I hope this will help, if not try to elaborate your issue.
Thanks,
Istvan