Dragos,
Thanks for the testing.
On my AD-FMCCOMMS4-EBZ the tx still inverted, and there is no change if I manually set the Invert TX1 bit from register 011. Here I attach my init parameters and dev (dev_err, dev_warn, dev_dbg) log, could you please help to check if anything wrong?
BTW, could you please send me the dev print log when calling ad9361_init()? I will try to check the difference between my AD9364 initialization and yours.
Regards
Jimmy
1. init parameters:
AD9361_InitParam default_init_param = {
/* Identification number */
0, //id_no;
/* Reference Clock */
40000000UL, //reference_clk_rate
/* Base Configuration */
0, //two_rx_two_tx_mode_enable *** adi,2rx-2tx-mode-enable 1 for 9361, 0 for 9364
1, //frequency_division_duplex_mode_enable *** adi,frequency-division-duplex-mode-enable --> REG_ENSM_MODE==0x013[0]
0, //frequency_division_duplex_independent_mode_enable *** adi,frequency-division-duplex-independent-mode-enable
1, //tdd_use_dual_synth_mode_enable *** adi,tdd-use-dual-synth-mode-enable --> REG_ENSM_CONFIG_2[2]==0x015[2]
0, //tdd_skip_vco_cal_enable *** adi,tdd-skip-vco-cal-enable
0, //tx_fastlock_delay_ns *** adi,tx-fastlock-delay-ns
0, //rx_fastlock_delay_ns *** adi,rx-fastlock-delay-ns
0, //rx_fastlock_pincontrol_enable *** adi,rx-fastlock-pincontrol-enable
0, //tx_fastlock_pincontrol_enable *** adi,tx-fastlock-pincontrol-enable
0, //external_rx_lo_enable *** adi,external-rx-lo-enable
0, //external_tx_lo_enable *** adi,external-tx-lo-enable
5, //dc_offset_tracking_update_event_mask *** adi,dc-offset-tracking-update-event-mask --> REG_DC_OFFSET_CONFIG2[2:0]==0x18B[2:0]
6, //dc_offset_attenuation_high_range *** adi,dc-offset-tracking-update-event-mask --> REG_RF_DC_OFFSET_ATTEN[4:0] == 0x188[4:0]
5, //dc_offset_attenuation_low_range *** adi,dc-offset-tracking-update-event-mask --> REG_RF_DC_OFFSET_ATTEN[4:0] == 0x188[4:0]
0x28, //dc_offset_count_high_range *** adi,dc-offset-tracking-update-event-mask --> REG_RF_DC_OFFSET_COUNT[7:0] == 0x186[7:0] , when ref>40MHz
0x32, //dc_offset_count_low_range *** adi,dc-offset-tracking-update-event-mask --> REG_RF_DC_OFFSET_COUNT[7:0] == 0x186[7:0] , when ref<40MHz
0, //tdd_use_fdd_vco_tables_enable *** adi,tdd-use-fdd-vco-tables-enable
0, //split_gain_table_mode_enable *** adi,split-gain-table-mode-enable 0
MAX_SYNTH_FREF, //trx_synthesizer_target_fref_overwrite_hz *** adi,trx-synthesizer-target-fref-overwrite-hz
0, // qec_tracking_slow_mode_enable *** adi,qec-tracking-slow-mode-enable
/* ENSM Control */
0, //ensm_enable_pin_pulse_mode_enable *** adi,ensm-enable-pin-pulse-mode-enable --> REG_ENSM_CONFIG_1[3] == 0x014[3]
0, //ensm_enable_txnrx_control_enable *** adi,ensm-enable-txnrx-control-enable REG_ENSM_CONFIG_2[3] == 0x015[3]
/* LO Control */
2398000000UL, //rx_synthesizer_frequency_hz *** adi,rx-synthesizer-frequency-hz
2402000000UL, //tx_synthesizer_frequency_hz *** adi,tx-synthesizer-frequency-hz
/* Rate & BW Control */
// BBPLL_FREQ ADC_FREQ R2_FREQ R1_FREQ CLKRF_FREQ RX_SAMPL_FREQ
// 715M < BBPLL_FREQ < 1430M
// 11.17M < ADC_FREQ < 640M
// R2_FREQ-> provides clock for HB3/DEC3, deimated by 2 or 3, or bypassed
// R1_FREQ-> provides clock for HB2, decimate by 2, or bypassed
// CLKRF_FREQ-> provides clock for HB1, decimate by 2 or bypassed
// RX_SAMPL_FREQ -> provides clock for fir, can decimate by 1, 2 or 4, or bypassed
//8m
//{1024000000, 64000000, 32000000, 16000000, 8000000, 4000000},//uint32_t rx_path_clock_frequencies[6] *** adi,rx-path-clock-frequencies 4000000
// IGNORE, DAC_FREQ, T2_FREQ, T1_FREQ, CLKTF_FREQ, TX_SAMPL_FREQ
{1024000000, 128000000, 64000000, 32000000, 16000000, 16000000},//uint32_t rx_path_clock_frequencies[6] *** adi,rx-path-clock-frequencies
////{1024000000, 256000000, 128000000, 64000000, 32000000, 32000000},//uint32_t rx_path_clock_frequencies[6] *** adi,rx-path-clock-frequencies
// IGNORE, DAC_FREQ, T2_FREQ, T1_FREQ, CLKTF_FREQ, TX_SAMPL_FREQ
// DAC_FREQ=ADC_FREQ /(1 or 2)
// T2_FREQ --> provides clock for HB3/INT3, interpolate by 2 or 3 or bypassed
// T1_FREQ --> provides clock for HB2, interpolate by 2 or bypassed
// CLKTF_FREQ --> provides clock for HB1, interpolate by 2 or bypassed
// TX_SAMPL_FREQ --> provides clock for fir, can interpolate by 1, 2 or 4, or bypassed
//8m
//{1024000000, 64000000, 32000000, 16000000, 8000000, 4000000},//uint32_t tx_path_clock_frequencies[6] *** adi,tx-path-clock-frequencies 4000000
{1024000000, 128000000, 64000000, 32000000, 16000000, 16000000},//uint32_t tx_path_clock_frequencies[6] *** adi,tx-path-clock-frequencies
////{1024000000, 256000000, 128000000, 64000000, 32000000, 32000000},//uint32_t tx_path_clock_frequencies[6] *** adi,tx-path-clock-frequencies
8000000,//rf_rx_bandwidth_hz *** adi,rf-rx-bandwidth-hz
////16000000,//rf_rx_bandwidth_hz *** adi,rf-rx-bandwidth-hz
2000000,//rf_tx_bandwidth_hz *** adi,rf-tx-bandwidth-hz
/* RF Port Control */
1, //rx_rf_port_input_select *** adi,rx-rf-port-input-select --> REG_INPUT_SELECT =0x004[5:0], 0->Rx1A, 1->Rx1B, 2->Rx1C
1, //tx_rf_port_input_select *** adi,tx-rf-port-input-select --> REG_INPUT_SELECT =0x004[6], 1=TxB port
/* TX Attenuation Control */
6000, //tx_attenuation_mdB *** adi,tx-attenuation-mdB --> REG_TX2_DIG_ATTEN={0x074[0],0x073[7:0]} 00000 12000
0, //update_tx_gain_in_alert_enable *** adi,update-tx-gain-in-alert-enable
/* Reference Clock Control */
0, //xo_disable_use_ext_refclk_enable *** adi,xo-disable-use-ext-refclk-enable --> REG_CLOCK_ENABLE = 0x009[4]
{8, 5500}, //dcxo_coarse_and_fine_tune[2] *** adi,dcxo-coarse-and-fine-tune --> {REG_DCXO_COARSE_TUNE , {REG_DCXOFINE_TUNE_HIGH,REG_DCXO_FINE_TUNE_LOW}}={0x292, {0x293,0x294}}
0, //clk_output_mode_select *** adi,clk-output-mode-select --> REG_BBPLL[4] = 0x00A[4]
/* Gain Control */
0, //gc_rx1_mode *** adi,gc-rx1-mode 2-slow attack, 1-fast agc, 0-MGC
2, //gc_rx2_mode *** adi,gc-rx2-mode
58, //gc_adc_large_overload_thresh *** adi,gc-adc-large-overload-thresh
4, //gc_adc_ovr_sample_size *** adi,gc-adc-ovr-sample-size
47, //gc_adc_small_overload_thresh *** adi,gc-adc-small-overload-thresh
8192, //gc_dec_pow_measurement_duration *** adi,gc-dec-pow-measurement-duration
0, //gc_dig_gain_enable *** adi,gc-dig-gain-enable
800, //gc_lmt_overload_high_thresh *** adi,gc-lmt-overload-high-thresh
704, //gc_lmt_overload_low_thresh *** adi,gc-lmt-overload-low-thresh
24, //gc_low_power_thresh *** adi,gc-low-power-thresh
15, //gc_max_dig_gain *** adi,gc-max-dig-gain
/* Gain MGC Control */
0, //mgc_dec_gain_step *** adi,mgc-dec-gain-step 2
0, //mgc_inc_gain_step *** adi,mgc-inc-gain-step 2
0, //mgc_rx1_ctrl_inp_enable *** adi,mgc-rx1-ctrl-inp-enable
0, //mgc_rx2_ctrl_inp_enable *** adi,mgc-rx2-ctrl-inp-enable
0, //mgc_split_table_ctrl_inp_gain_mode *** adi,mgc-split-table-ctrl-inp-gain-mode
/* Gain AGC Control */
10, //agc_adc_large_overload_exceed_counter *** adi,agc-adc-large-overload-exceed-counter
2, //agc_adc_large_overload_inc_steps *** adi,agc-adc-large-overload-inc-steps
0, //agc_adc_lmt_small_overload_prevent_gain_inc_enable *** adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable
10, //agc_adc_small_overload_exceed_counter *** adi,agc-adc-small-overload-exceed-counter
4, //agc_dig_gain_step_size *** adi,agc-dig-gain-step-size
3, //agc_dig_saturation_exceed_counter *** adi,agc-dig-saturation-exceed-counter
3000, // agc_gain_update_interval_us *** adi,agc-gain-update-interval-us
0, //agc_immed_gain_change_if_large_adc_overload_enable *** adi,agc-immed-gain-change-if-large-adc-overload-enable
0, //agc_immed_gain_change_if_large_lmt_overload_enable *** adi,agc-immed-gain-change-if-large-lmt-overload-enable
10, //agc_inner_thresh_high *** adi,agc-inner-thresh-high
1, //agc_inner_thresh_high_dec_steps *** adi,agc-inner-thresh-high-dec-steps
12, //agc_inner_thresh_low *** adi,agc-inner-thresh-low
1, //agc_inner_thresh_low_inc_steps *** adi,agc-inner-thresh-low-inc-steps
10, //agc_lmt_overload_large_exceed_counter *** adi,agc-lmt-overload-large-exceed-counter
2, //agc_lmt_overload_large_inc_steps *** adi,agc-lmt-overload-large-inc-steps
10, //agc_lmt_overload_small_exceed_counter *** adi,agc-lmt-overload-small-exceed-counter
5, //agc_outer_thresh_high *** adi,agc-outer-thresh-high
2, //agc_outer_thresh_high_dec_steps *** adi,agc-outer-thresh-high-dec-steps
18, //agc_outer_thresh_low *** adi,agc-outer-thresh-low
2, //agc_outer_thresh_low_inc_steps *** adi,agc-outer-thresh-low-inc-steps
1, //agc_attack_delay_extra_margin_us; *** adi,agc-attack-delay-extra-margin-us
0, //agc_sync_for_gain_counter_enable *** adi,agc-sync-for-gain-counter-enable
/* Fast AGC */
64, //fagc_dec_pow_measuremnt_duration *** adi,fagc-dec-pow-measurement-duration
260, //fagc_state_wait_time_ns *** adi,fagc-state-wait-time-ns
/* Fast AGC - Low Power */
0, //fagc_allow_agc_gain_increase *** adi,fagc-allow-agc-gain-increase-enable
5, //fagc_lp_thresh_increment_time *** adi,fagc-lp-thresh-increment-time
1, //fagc_lp_thresh_increment_steps *** adi,fagc-lp-thresh-increment-steps
/* Fast AGC - Lock Level */
10, //fagc_lock_level *** adi,fagc-lock-level */
1, //fagc_lock_level_lmt_gain_increase_en *** adi,fagc-lock-level-lmt-gain-increase-enable
5, //fagc_lock_level_gain_increase_upper_limit *** adi,fagc-lock-level-gain-increase-upper-limit
/* Fast AGC - Peak Detectors and Final Settling */
1, //fagc_lpf_final_settling_steps *** adi,fagc-lpf-final-settling-steps
1, //fagc_lmt_final_settling_steps *** adi,fagc-lmt-final-settling-steps
3, //fagc_final_overrange_count *** adi,fagc-final-overrange-count
/* Fast AGC - Final Power Test */
0, //fagc_gain_increase_after_gain_lock_en *** adi,fagc-gain-increase-after-gain-lock-enable
/* Fast AGC - Unlocking the Gain */
/* 0 = MAX Gain, 1 = Optimized Gain, 2 = Set Gain */
0, //fagc_gain_index_type_after_exit_rx_mode *** adi,fagc-gain-index-type-after-exit-rx-mode
1, //fagc_use_last_lock_level_for_set_gain_en *** adi,fagc-use-last-lock-level-for-set-gain-enable
1, //fagc_rst_gla_stronger_sig_thresh_exceeded_en *** adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable
5, //fagc_optimized_gain_offset *** adi,fagc-optimized-gain-offset
10, //fagc_rst_gla_stronger_sig_thresh_above_ll *** adi,fagc-rst-gla-stronger-sig-thresh-above-ll
1, //fagc_rst_gla_engergy_lost_sig_thresh_exceeded_en *** adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable
1, //fagc_rst_gla_engergy_lost_goto_optim_gain_en *** adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable
10, //fagc_rst_gla_engergy_lost_sig_thresh_below_ll *** adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll
8, //fagc_energy_lost_stronger_sig_gain_lock_exit_cnt *** adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt
1, //fagc_rst_gla_large_adc_overload_en *** adi,fagc-rst-gla-large-adc-overload-enable
1, //fagc_rst_gla_large_lmt_overload_en *** adi,fagc-rst-gla-large-lmt-overload-enable
0, //fagc_rst_gla_en_agc_pulled_high_en *** adi,fagc-rst-gla-en-agc-pulled-high-enable
0, //fagc_rst_gla_if_en_agc_pulled_high_mode *** adi,fagc-rst-gla-if-en-agc-pulled-high-mode
64, //fagc_power_measurement_duration_in_state5 *** adi,fagc-power-measurement-duration-in-state5
/* RSSI Control */
1, //rssi_delay *** adi,rssi-delay
1000, //rssi_duration *** adi,rssi-duration
3, //rssi_restart_mode *** adi,rssi-restart-mode
0, //rssi_unit_is_rx_samples_enable *** adi,rssi-unit-is-rx-samples-enable
1, //rssi_wait *** adi,rssi-wait
/* Aux ADC Control */
256, //aux_adc_decimation *** adi,aux-adc-decimation
40000000UL, //aux_adc_rate *** adi,aux-adc-rate
/* AuxDAC Control */
1, //aux_dac_manual_mode_enable *** adi,aux-dac-manual-mode-enable
0, //aux_dac1_default_value_mV *** adi,aux-dac1-default-value-mV
0, //aux_dac1_active_in_rx_enable *** adi,aux-dac1-active-in-rx-enable
0, //aux_dac1_active_in_tx_enable *** adi,aux-dac1-active-in-tx-enable
0, //aux_dac1_active_in_alert_enable *** adi,aux-dac1-active-in-alert-enable
0, //aux_dac1_rx_delay_us *** adi,aux-dac1-rx-delay-us
0, //aux_dac1_tx_delay_us *** adi,aux-dac1-tx-delay-us
0, //aux_dac2_default_value_mV *** adi,aux-dac2-default-value-mV
0, //aux_dac2_active_in_rx_enable *** adi,aux-dac2-active-in-rx-enable
0, //aux_dac2_active_in_tx_enable *** adi,aux-dac2-active-in-tx-enable
0, //aux_dac2_active_in_alert_enable *** adi,aux-dac2-active-in-alert-enable
0, //aux_dac2_rx_delay_us *** adi,aux-dac2-rx-delay-us
0, //aux_dac2_tx_delay_us *** adi,aux-dac2-tx-delay-us
/* Temperature Sensor Control */
256, //temp_sense_decimation *** adi,temp-sense-decimation
1000, //temp_sense_measurement_interval_ms *** adi,temp-sense-measurement-interval-ms
0xCE, //temp_sense_offset_signed *** adi,temp-sense-offset-signed
1, //temp_sense_periodic_measurement_enable *** adi,temp-sense-periodic-measurement-enable
/* Control Out Setup */
0xFF, //ctrl_outs_enable_mask *** adi,ctrl-outs-enable-mask
0, //ctrl_outs_index *** adi,ctrl-outs-index
/* External LNA Control */
0, //elna_settling_delay_ns *** adi,elna-settling-delay-ns
0, //elna_gain_mdB *** adi,elna-gain-mdB
0, //elna_bypass_loss_mdB *** adi,elna-bypass-loss-mdB
0, //elna_rx1_gpo0_control_enable *** adi,elna-rx1-gpo0-control-enable
0, //elna_rx2_gpo1_control_enable *** adi,elna-rx2-gpo1-control-enable
/* Digital Interface Control */
1, //digital_interface_tune_skip_mode *** adi,digital-interface-tune-skip-mode //0-no skip 1-skip tx 2-skip both and use default
1, //pp_tx_swap_enable *** adi,pp-tx-swap-enable --> REG_PARALLEL_PORT_CONF_1=0x010[7], 1=disable
1, //pp_rx_swap_enable *** adi,pp-rx-swap-enable --> REG_PARALLEL_PORT_CONF_1=0x010[6], 1=disable
0, //tx_channel_swap_enable *** adi,tx-channel-swap-enable --> REG_PARALLEL_PORT_CONF_1=0x010[5], 1=enable, must be 0
0, //rx_channel_swap_enable *** adi,rx-channel-swap-enable --> REG_PARALLEL_PORT_CONF_1=0x010[4], 1=enable, must be 0
0, //rx_frame_pulse_mode_enable *** adi,rx-frame-pulse-mode-enable --> REG_PARALLEL_PORT_CONF_1=0x010[3], 1=enable
0, //two_t_two_r_timing_enable *** adi,2t2r-timing-enable --> REG_PARALLEL_PORT_CONF_1=0x010[2], 1=enable
0, //invert_data_bus_enable *** adi,invert-data-bus-enable --> REG_PARALLEL_PORT_CONF_1=0x010[1], 1=enable, P0[11:0]->P0[0:11]
0, //invert_data_clk_enable *** adi,invert-data-clk-enable --> REG_PARALLEL_PORT_CONF_1=0x010[0], 1=enable
0, //fdd_alt_word_order_enable *** adi,fdd-alt-word-order-enable --> REG_PARALLEL_PORT_CONF_2=0x011[7], 1=enable, each port split into 6bit halves.
0, //invert_rx_frame_enable *** adi,invert-rx-frame-enable --> REG_PARALLEL_PORT_CONF_2=0x011[2], 1=enable
0, //fdd_rx_rate_2tx_enable *** adi,fdd-rx-rate-2tx-enable --> REG_PARALLEL_PORT_CONF_3=0x012[7], 1=enable
0, //swap_ports_enable *** adi,swap-ports-enable --> REG_PARALLEL_PORT_CONF_3=0x012[6], 1=swap port 0 and port 1
0, //single_data_rate_enable *** adi,single-data-rate-enable --> REG_PARALLEL_PORT_CONF_3=0x012[5], 1=use one clock edge (SDR)
0, //lvds_mode_enable *** adi,lvds-mode-enable --> REG_PARALLEL_PORT_CONF_3=0x012[4], 1=LVDS
0, //half_duplex_mode_enable *** adi,half-duplex-mode-enable --> REG_PARALLEL_PORT_CONF_3=0x012[3], 1=half duplex mode
0, //single_port_mode_enable *** adi,single-port-mode-enable --> REG_PARALLEL_PORT_CONF_3=0x012[2], 1=only P0 or P1 is used
1, //full_port_enable *** adi,full-port-enable --> REG_PARALLEL_PORT_CONF_3=0x012[1], 1=force receiver on 1 port, transmitter on the other port
0, //full_duplex_swap_bits_enable *** adi,full-duplex-swap-bits-enable --> REG_PARALLEL_PORT_CONF_3=0x012[0]
0, //delay_rx_data *** adi,delay-rx-data --> REG_PARALLEL_PORT_CONF_2=0x011[1:0]
0, //rx_data_clock_delay *** adi,rx-data-clock-delay --> REG_RX_CLOCK_DATA_DELAY =0x006[7:4]
4, //rx_data_delay *** adi,rx-data-delay --> REG_RX_CLOCK_DATA_DELAY =0x006[3:0]
7, //tx_fb_clock_delay *** adi,tx-fb-clock-delay --> REG_TX_CLOCK_DATA_DELAY =0x007[7:4]
0, //tx_data_delay *** adi,tx-data-delay --> REG_TX_CLOCK_DATA_DELAY =0x007[3:0]
150, //lvds_bias_mV *** adi,lvds-bias-mV --> REG_LVDS_BIAS_CTRL=0x03c[2:0]
0, //lvds_rx_onchip_termination_enable *** adi,lvds-rx-onchip-termination-enable --> REG_LVDS_BIAS_CTRL=0x03c[5], don't use it in CMOS mode
0, //rx1rx2_phase_inversion_en *** adi,rx1-rx2-phase-inversion-enable
/* Tx Monitor Control */
37000, //low_high_gain_threshold_mdB *** adi,txmon-low-high-thresh
0, //low_gain_dB *** adi,txmon-low-gain
24, //high_gain_dB *** adi,txmon-high-gain
0, //tx_mon_track_en *** adi,txmon-dc-tracking-enable
0, //one_shot_mode_en *** adi,txmon-one-shot-mode-enable
511, //tx_mon_delay *** adi,txmon-delay
8192, //tx_mon_duration *** adi,txmon-duration
2, //tx1_mon_front_end_gain *** adi,txmon-1-front-end-gain
2, //tx2_mon_front_end_gain *** adi,txmon-2-front-end-gain
48, //tx1_mon_lo_cm *** adi,txmon-1-lo-cm
48, //tx2_mon_lo_cm *** adi,txmon-2-lo-cm
/* GPIO definitions */
0xb5, //gpio_resetb; /* reset-gpios b5 */
/* MCS Sync */
-1, //gpio_sync; /* sync-gpios */
-1, //gpio_cal_sw1; /* cal-sw1-gpios */
-1 //gpio_cal_sw2; /* cal-sw2-gpios */
};
2. dev print log:
ad9361_reset: by GPIO
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_setup
ad9361_set_dcxo_tune : coarse 8 fine 5500
ad9361_set_trx_clock_chain
ad9361_set_trx_clock_chain: 1024000000 128000000 64000000 32000000 16000000 16000000
ad9361_set_trx_clock_chain: 1024000000 128000000 64000000 32000000 16000000 16000000
ad9361_bbpll_set_rate: Rate 1024000000 Hz Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_clk_factor_set_rate: Rate 16000000 Hz Parent Rate 16000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_clk_factor_set_rate: Rate 16000000 Hz Parent Rate 16000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rssi_setup
ad9361_auxadc_setup
ad9361_rf_port_setup : INPUT_SELECT 0x4c
ad9361_pp_port_setup
ad9361_auxdac_setup
ad9361_auxdac_set DAC1 = 0 mV
ad9361_auxdac_set DAC2 = 0 mV
ad9361_auxadc_setup
ad9361_ctrl_outs_setup
ad9361_gpo_setup
ad9361_set_ref_clk_cycles : ref_clk_hz 40000000
ad9361_txrx_synth_cp_calib : ref_clk_hz 40000000 : is_tx 0
ad9361_txrx_synth_cp_calib : ref_clk_hz 40000000 : is_tx 1
ad9361_rfpll_set_rate: Rate 1199000000 Hz Parent Rate 40000000 Hz
ad9361_fastlock_prepare: RX Profile 0: Un-Prepare
ad9361_rfpll_vco_init : vco_freq ERRORlu : ref_clk 1002065408 : range 2
ad9361_rfpll_vco_init : freq 9445 MHz : index 12
ad9361_load_gt: frequency ERRORlu
ad9361_load_gt: frequency ERRORlu (band -1896967296)
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_set_rate: Rate 1201000000 Hz Parent Rate 40000000 Hz
ad9361_fastlock_prepare: TX Profile 0: Un-Prepare
ad9361_rfpll_vco_init : vco_freq ERRORlu : ref_clk 1018065408 : range 2
ad9361_rfpll_vco_init : freq 9445 MHz : index 12
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_load_mixer_gm_subtable
ad9361_gc_setup
ad9361_rx_bb_analog_filter_calib : rx_bb_bw 4000000 bbpll_freq 1024000000
ad9361_run_calibration: CAL Mask 0x80
ad9361_tx_bb_analog_filter_calib : tx_bb_bw 1000000 bbpll_freq 1024000000
ad9361_run_calibration: CAL Mask 0x40
ad9361_rx_tia_calib : bb_bw_Hz 4000000
ad9361_tx_bb_second_filter_calib : tx_bb_bw 1000000
ad9361_rx_adc_setup : BBBW 3842364 : ADCfreq 128000000
c3_msb 0x0 : c3_lsb 0x41 : r2346 0x2 :
invrc_tconst_1e6 ERRORlu, sqrt_inv_rc_tconst_1e3 0
scaled_adc_clk_1e6 200000, inv_scaled_adc_clk_1e3 5000
tmp_1e3 1005, sqrt_term_1e3 447, min_sqrt_term_1e3 894
ad9361_bb_dc_offset_calib
ad9361_run_calibration: CAL Mask 0x1
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rf_dc_offset_calib : rx_freq ERRORlu
ad9361_run_calibration: CAL Mask 0x2
ad9361_tx_quad_calib : bw_tx 1000000 clkrf 16000000 clktf 16000000
Tx NCO frequency: 500000 (BW/4: 250000) txnco_word 0
__ad9361_update_rf_bandwidth: 4000000 4000000
ad9361_rx_bb_analog_filter_calib : rx_bb_bw 2000000 bbpll_freq 1024000000
ad9361_run_calibration: CAL Mask 0x80
ad9361_tx_bb_analog_filter_calib : tx_bb_bw 2000000 bbpll_freq 1024000000
ad9361_run_calibration: CAL Mask 0x40
ad9361_rx_tia_calib : bb_bw_Hz 2000000
ad9361_tx_bb_second_filter_calib : tx_bb_bw 2000000
ad9361_rx_adc_setup : BBBW 1968040 : ADCfreq 128000000
c3_msb 0x3 : c3_lsb 0xd : r2346 0x4 :
invrc_tconst_1e6 ERRORlu, sqrt_inv_rc_tconst_1e3 0
scaled_adc_clk_1e6 200000, inv_scaled_adc_clk_1e3 5000
tmp_1e3 1005, sqrt_term_1e3 447, min_sqrt_term_1e3 894
ad9361_run_calibration: CAL Mask 0x10
LO leakage: 1 Quadrature Calibration: 1 : rx_phase 21
txnco_freq: 500000,bw_rx:4000000,bw_tx: 1000000,current_rx_bw_Hz:0,phy->current_tx_bw_Hz:0
__ad9361_update_rf_bandwidth: 0 0
ad9361_rx_bb_analog_filter_calib : rx_bb_bw 0 bbpll_freq 1024000000
ad9361_run_calibration: CAL Mask 0x80
ad9361_tx_bb_analog_filter_calib : tx_bb_bw 0 bbpll_freq 1024000000
ad9361_run_calibration: CAL Mask 0x40
ad9361_rx_tia_calib : bb_bw_Hz 0
ad9361_tx_bb_second_filter_calib : tx_bb_bw 0
ad9361_rx_adc_setup : BBBW 199726 : ADCfreq 128000000
c3_msb 0x30 : c3_lsb 0x3 : r2346 0x4 :
invrc_tconst_1e6 ERRORlu, sqrt_inv_rc_tconst_1e3 0
scaled_adc_clk_1e6 200000, inv_scaled_adc_clk_1e3 5000
tmp_1e3 1005, sqrt_term_1e3 447, min_sqrt_term_1e3 894
ad9361_tracking_control : bbdc_track=1, rfdc_track=1, rxquad_track=1
ad9361_pp_port_setup
ad9361_set_tx_atten : attenuation 6000 mdB tx1=1 tx2=1
ad9361_rssi_setup
ad9361_txmon_setup
Device is in 5 state, moving to a
ad9361_bist_prbs: mode 2
ad9361_calculate_rf_clock_chain: requested rate 10000000 TXFIR int 1 RXFIR dec 1 mode Nominal
ad9361_set_trx_clock_chain
ad9361_set_trx_clock_chain: 1280000000 80000000 40000000 20000000 10000000 10000000
ad9361_set_trx_clock_chain: 1280000000 80000000 40000000 20000000 10000000 10000000
ad9361_bbpll_set_rate: Rate 1280000000 Hz Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_clk_factor_set_rate: Rate 80000000 Hz Parent Rate 1280000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rssi_setup
ad9361_auxadc_setup
ad9361_calculate_rf_clock_chain: requested rate 32000000 TXFIR int 1 RXFIR dec 1 mode Nominal
ad9361_set_trx_clock_chain
ad9361_set_trx_clock_chain: 1024000000 256000000 128000000 64000000 32000000 32000000
ad9361_set_trx_clock_chain: 1024000000 256000000 128000000 64000000 32000000 32000000
ad9361_bbpll_set_rate: Rate 1024000000 Hz Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_clk_factor_set_rate: Rate 256000000 Hz Parent Rate 1024000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rssi_setup
ad9361_auxadc_setup
ad9361_dig_tune: Tuning RX FAILED!
ad9361_bist_prbs: mode 0
ad9361_bist_loopback: mode 1
ad9361_calculate_rf_clock_chain: requested rate 10000000 TXFIR int 1 RXFIR dec 1 mode Nominal
ad9361_set_trx_clock_chain
ad9361_set_trx_clock_chain: 1280000000 80000000 40000000 20000000 10000000 10000000
ad9361_set_trx_clock_chain: 1280000000 80000000 40000000 20000000 10000000 10000000
ad9361_bbpll_set_rate: Rate 1280000000 Hz Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_clk_factor_set_rate: Rate 80000000 Hz Parent Rate 1280000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rssi_setup
ad9361_auxadc_setup
ad9361_calculate_rf_clock_chain: requested rate 32000000 TXFIR int 1 RXFIR dec 1 mode Nominal
ad9361_set_trx_clock_chain
ad9361_set_trx_clock_chain: 1024000000 256000000 128000000 64000000 32000000 32000000
ad9361_set_trx_clock_chain: 1024000000 256000000 128000000 64000000 32000000 32000000
ad9361_bbpll_set_rate: Rate 1024000000 Hz Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_clk_factor_set_rate: Rate 256000000 Hz Parent Rate 1024000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rssi_setup
ad9361_auxadc_setup
ad9361_bist_loopback: mode 0
ad9361_set_trx_clock_chain
ad9361_set_trx_clock_chain: 1024000000 128000000 64000000 32000000 16000000 16000000
ad9361_set_trx_clock_chain: 1024000000 128000000 64000000 32000000 16000000 16000000
ad9361_clk_factor_set_rate: Rate 128000000 Hz Parent Rate 1024000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rssi_setup
ad9361_auxadc_setup
(Notes: "ad9361_dig_tune: Tuning RX FAILED!" this happened also in the old version software while tx and rx both worked well)