Here is an optimized version that includes memory address calculation. I realized it was more efficient for both memory use and instructions to go to three downsamples in six sample periods, so the function is now:
0 send read command / read downsample 1
1 read downsamples 2-3
2 CS high (terminates read command)
3 send write command / write downsample 1
4 write downsamples 2-3
5 CS high (terminates write command)
It may be a good idea to hold CS high for an initial run through the memory cycle (682ms max @ 48), and probably mute the output as it would not be reliable for the first cycle. I'll test that when I can get an SRAM hooked up to my eval kit. I don't think SRAM initialization beyond that would be necessary as the chip defaults to sequential read/write mode, which is what we want.
Another possibility for external SRAM would be storing samples, this would be easier and thus take fewer instructions, since read and write mode could be externally triggered, and just run sequentially until stopped. And it wouldn't have to be downsampled unless desired. The maximum sample storage is still 16K; since the default mode would record/playback in stereo, it might be necessary to implement the SRAM's Hold feature if full use of the 16K samples was desired for a mono signal.