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Re: ADF4351 settling time calculation using teh EVAL baords

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I forgot that the band select clock time in R4 should be set to 500 kHz. This works in conjunction with setting the band select clock mode high. Try these settings:

  • I set your channel spacing to 500 kHz so the MOD value would be set to 50. When using Low Spur Mode, MOD must be 50 or greater.
  • I unchecked the band select clock auto set and set manually set the divider to 50. This speeds up the band select process from 80 µs to 20 µs. (I will update the software to auto set to 500 kHz. Update: done here.)

 

Lock Detect is asserted when the frequency error at the R and N inputs of the PFD is less than a certain window. As the loop approaches lock, the frequency error slips in and out of the window until fully settling inside the window. This results in the high and low signals you are seeing. Try changing LDP in Register 2 to see if this has an impact.

 

If changing the band select divider doesn't give the required settling time, I'll design a new loop filter, test it in our lab, and send you the results.


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