I have been able to get the design to work in Vivado 2014.2 and 2014.3. The main key was that when upgrading to 2014.2, I had to add the line "set_property -dict [list CONFIG.C_AUX_RESET_HIGH {0}] $sys_rstgen" to the block diagram TCL file
I discovered this by using Xilinx 2014.2 to upgrade my 2014.1 project (as opposed to just replacing the IP version numbers in the TCL scripts and regenerating the whole project) and it worked that way. I then exported the Block Diagram to TCL and saw this new line.
I didn't have to do anything to go from 2014.2 to 2014.3 other than change the PS IP from 5.4 to 5.5.
Vivado 2014.3 has a great new feature where you can regenerate a project but don't have to regenerate the IP cores, which is like a 30 minute process.