HI Lionel,
Have you tried connecting at J9 without probing it. We're suspecting that it has something to do with your setup or the quality of cables that you are using. Checking at the last picture, the minimum peak voltage is at 1.3 V which is very high, that will cause problem to the LVCMOS33 spec on VIL. Although the signal is attenuated, the offset voltlage is very high. We did a setup that is similar to yours and we got this result.
We used two cables and they are all connected to SYNC_CLK. Both signals were terminated with 1 Mohm impedance. However their peak to peak values weren't the same. In addition, we noticed that the attenuation varies depending on the orientation or position of the cables. Going back to the picture, it seems that the signal suffered a lot of distortions, I'm suspecting that it might be due to the cables. Try improving the setup first, I hope the clock signal would improve.
Regards
Louijie