Hi Jetmir,
rx_data_clock_delay and rx_data_delay settings affect the DATA_CLK and the Rx Data delays. If the two values are equal, then the data bits will approximately align with the DATA_CLK edge.
For tx_fb_clock_delay and tx_data_delay the description is the same, but these settings affect FB_CLK and Tx Data delays.
Please take a look on the wiki: AD9361 Device Driver Customization [Analog Devices Wiki] and on the AD9361 manual for more information.
Thanks,
Dragos