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Re: Is AD9910 IO_UPDATE line gated by chip select?

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Hi David,

 

You can refer to this circuit note for reference on multiple chip sync on AD9910s: Circuit Note | CN0121 | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers | Analog Devices

DDS cores has I/O buffered register and active registers.

The serial write (SDIO, SCLK, -CS) only writes to the inactive register  (I/O buffer) of the DDS.

The I/O_UPDATE is a different input. A rising edge on I/O_UPDATE initiates a transfer from inactive register to active register. You can refer to page 42 of AD9910 datasheet.

What we recommend, is write first on the I/O buffer, before sending all the register values to the active registers.


Is the IO UPDATE line enabled by chip select?

So, it is better not to enable I/O_UPDATE thru chip select because you need to consider the hold-time and set-up time of I/O_UPDATE with respect to SYNC_CLK.

The recommended setting would be, to have a different control for I/O_UPDATE. You can serially write to all DDSs and then, issue I/O_UPDATE to all DDSs.


Can several AD9910s share a common IO UPDATE line?

Yes you can, as long as your microcontroller GPIO current limit is set to drive all the AD9910 I/O_UPDATE input. The logic 1 current for each AD9910 has max value of 150uA.

IF not, I suggest you use a buffer or CMOS driver before sending the I/O_UPDATE signal to make sure you have enough drive capability. This will also serve as protection, allowing isolation of output/input of the system.


Hope this helps.


-Sittie


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