Re: [Need help]: something about the OSD menu postion and size
HI Jeyasudha.M： thank you for your warm heart help and i think i got the points. i will close the issue. BRXutao
View ArticleRe: About FSK Modulation at HMC703-EVB
Hi Dean-san,Thank you for giving information and teaching.Maybe, I will receive new question from the customer soon.So, please support me again later.BR, Tomo
View ArticleAbout Inside Resistance of HMC997LC4
Please tell me the inside resistance of HMC997LC4.The customer wants to know the inside resistance between Vctrl-pin and GND.Because he will use the external resister to input the divided voltage into...
View ArticleCan adv7181c detect resolution of rgb signal?
Hl I'm using adv7181c to convert rgb signal. The input signal may be 1024*768 or 800*600 rgb signal. I'm wondering if adv7181c can detect the resolution of input rgb signal. Thanks! zhou
View ArticleAD9625 modes of operation
Hi, A customer of mine is seeking to reduce the number of JESD204B lanes in which he needs to interface his FPGA to the AD9625. The reason is due to the pricing of the FPGA. If he can interface to the...
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Re: ADP1055 Digital Controller for Power Supply
Hi Philip, I have sent you the material, please check it. Please let me know if you have more question. If you want to use ADP1055 GUI, you cannot use other normal USB to I2C connector. The reason is...
View ArticleAD1974 Daisy-chain mode
Hello, My question pertains to connecting the clocks on a daisy-chained pair of AD1974 ADCs. My design uses 2 pairs of daisy-chained ADCs to create two TDM8 bitstreams to go into two of the I2S inputs...
View ArticleRe: ucLinux boot fails on Finboard
Hi Misra, this forum is really not good at support finboard that's designed by third party, have you tried to get support from the finboard website FinBoard? Yet this error comes from...
View ArticleRe: u-boot for BF707 EZ-Board available?
Hi Matt, reviewing the recent EZ threads you will find third party, DAB Embedded, is working on u-boot and Linux for BF707-ezkit, they have attached both binaries here, there is also a conversation...
View ArticleRe: u-boot for BF707 EZ-Board available?
U-boot for BF707-EZKIT For u-bootuClinux for BF707-EZKIT For Linux
View ArticleRe: ADP1048 bridgeless design
Hi Mack, There is no real issue. In the interleaved PFC, the phase current balancing is needed. If you swap the PWM output signals, the phase imbalance will be even worse. However, it looks to me no...
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Re: ADP1048 bridgeless design
Not a problem. However, you'll have to tweak the IBAL pin so that it knows which PWM to fire. See attached diagram:
View ArticleUsing external spdif tranceivers with ADAU1452
Hello, My questions pertains to clock connections on the ADAU1452 when using external spdif transceivers. My design requires 2 spdif inputs and outputs to be processed by the ADAU1452. I have elected...
View ArticleRe: AD8250 Reference Drive
Hi Ahmet, Thanks for including your schematic file. I will check your circuit and get back to you soon. Thanks!Kris
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ADIS16365 accelerometer null bias issue
Hello Sir, I am ADI FAE now supporting a ESP project, where ADIS16365 is used as benchmark to test ADXC1501, both ADIS16365 & ADXC1501 are placed & mounted on the same object, the signal chain...
View ArticleRe: Programming ad5752 in 2s comp mode
Hi, moynul islam. You may change your output range to +/-5V by changing the OUTPUT RANGE SELECT REGISTER. You have to set the values of the R2 to 0, R1 to 1, and R0 to1. You may refer to Table 21 and...
View ArticleRe: ADuM3150 datasheet
Hello, MSCantrell-san,Thank you very much for your prompt reply.I understood that. Best regards,Sofy
View ArticleADV7480 without audio output
Hello In my project,I use the ADV7480 as the hdmi sink.But I can't get any audio .The video is ok.I found that the LRCK=17.47k BCK=1.12M For question:1.Is it the problem of source's CTS&N value(I...
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Re: ADAU1761 Problems: PLL and Alias
Hello Philipp, The 1761's versatile PLL allows using a MCLK range from 8 to 27 MHz while maintaining a core clock of approx. 45 to 49 MHz. When the PLL is in use, the core clock is always...
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