So we have new information on the problem.
1) The cable we are using appears to have a low ohm to ground short (40 ohms) on the non-inverted HDMI signals. We went out and purchased two additional cables one of which showed the differential signals as open to gnd and the other that showed a similar issue low ohm short to ground (1 ohm). The cables with the "shorted" non inverting signal do allow a video signal to show up while the "non-shorted" cable has no image on the monitor. We will be passing this information on to the FPGA programmer to see about what may be happening in the data/clock signal.
2) the signals on the cable that appears to be correct, non-shorted to ground, now has something like a differential signal on it but the halves are not biased at the same level.
Inverted signal is biased at 2.5 VDC with a swing of approximately -0.35 / +0.25 volt
Non inverted signal is biased at 550 mV with a swing of -190 mV / + 220 mV
2a) The signals with the cable that appears to have a low ohm short are
Inverted signal is biased at 2.25 volt with a similar voltage swing as above
Non - inverted signal is sitting less than 100 mV with no discernible signal present
3) While the cable that has the "differential" signal does not develop an image on the monitor; Placing a scope probe on the clock, potentially skewing the clock, an image will briefly appear. This is the mode that we sill have the FPGA programmer look into.
So the question now is
Why would cables demonstrate different loads to the chip?
and
How is clock phase related to the parallel input data stream?
How is this phase manifested in the output data stream?
Thanks
D.