I applied a 800usec clock whenever the chip was idle. DIN was high. So, I always reset the chip.
I changed the code to reset the chip not so often, but the problem still happens
The following is the procedure I read the mode register.
1. Give CLK for 32 times with high DIN.
2. Wait 300msec with high DIN and high CLK
3. Give 8 clocks with DIN of 0x12 (single read of model register)
4. Wait 3.5ms with high DIN and high CLK
5. Give 16 clocks with high DIN. During the clock, read DOUT
6. Wait 600ms, and repeat from 1.
16bit DOUT read in the procedure 5 was 0x140.
I bought two AD7730 evaluation boards, and both of them show the same value.
I wonder whether my jumper configuration is right. Also, I wonder how long should I wait after the reset to read a valid mode register value? I think 300msec is enough.
I attached the signal during reading mode register and resetting.
I measured all the 24pins during the operation.
1. SCLK: 800usec 5V clock
2. MCLK IN: 2V constant
3. MCLK OUT: 1~3V 4.7MHz clock
4. POL: 5V
5. SYNC: 5V
6. RESET: 5V
7. V_BIAS: 0V
8. AGND: 0V
9. AVDD: 0V
10. AIN1+: 0V
11. AIN1-: 0V
12. AIN2(+): 0V
13. AIN2(-): 0V
14: REF IN(+): 0V
15: REF IN(-): 0V
16: ACX: 0V
17: /ACX: 0V
18: /STANDBY: 0V
19: /CS: (shown in picture)
20: /RDY: 5V
21: DOUT: (shown in picture)
22: DIN: (shown in picture)
23: DVDD: 5V
24: DGND: 0V
REF IN+ and AVDD is 0V because I didn't connect anything except the 9-pin connector. I already connected DVDD, AVDD, REF IN+ together, but nothing changed.
Thank you,
Kwan Suk Kim