Lars,
These are the complete and only modifications I made in the files:
No | File name | Line number | parameter | before | After |
1 | axi_ad9122_v2_1_0.mpd | 36 | C_DMA_BUS_WIDTH | 64 | 128 |
2 | axi_ad9122.v | 105 | C_DMA_BUS_WIDTH | 64 | 128 |
3 | axi_ad9122_core.v | 106 | C_DMA_BUS_WIDTH | 64 | 128 |
4 | axi_dmac_v2_1_0.mpd | 52 | C_DMA_DATA_WIDTH_DEST | 64 | 128 |
5 | 53 | C_DMA_DATA_WIDTH_SRC | 64 | 128 | |
6 | 28 | C_M_DEST_AXI_DATA_WIDTH | 64 | 128 | |
7 | address_generator.v | 68 | C_DMA_DATA_WIDTH | 64 | 128 |
8 | axi_dmac.v | 141 | C_DMA_DATA_WIDTH_SRC | 64 | 128 |
9 | 142 | C_DMA_DATA_WIDTH_DEST | 64 | 128 | |
10 | data_mover.v | 66 | C_DATA_WIDTH | 64 | 128 |
11 | dest_axi_mm.v | 97 | C_DMA_DATA_WIDTH | 64 | 128 |
12 | dest_axi_stream.v | 73 | C_S_AXIS_DATA_WIDTH | 64 | 128 |
13 | dest_fifo_inf.v | 74 | C_DATA_WIDTH | 64 | 128 |
14 | request_arb.v | 138 | C_DMA_DATA_WIDTH_SRC | 64 | 128 |
15 | 139 | C_DMA_DATA_WIDTH_DEST | 64 | 128 | |
16 | src_axi_mm.v | 88 | C_DMA_DATA_WIDTH | 64 | 128 |
17 | src_axi_stream.v | 68 | C_S_AXIS_DATA_WIDTH | 64 | 128 |
18 | src_fifo_inf.v | 68 | C_DATA_WIDTH | 64 | 128 |
19 | axi_repack.v | 52 | C_M_DATA_WIDTH | 64 | 128 |
20 | 53 | C_S_DATA_WIDTH | 64 | 128 |
A few questions:
- C_S_AXIS_DATA_WIDTH (item 12): should change or not?
- C_BEATS_PER_BURST_WIDTH (in dest_axi_stream.v): should remain =4 or not?
- What about the memory side? Any change regarding axi_dma_mm/ddr controller? I'm using ZC706.
- Where to modify the buffer length?
Best Regards,
FArid