Hi Cien and Jonathan,
The AD9523 will be able to do this conversion and I believe most of your settings are correct. One limitation in your frequency translation will be that the internal VCO in the AD9523 has a limited frequency range (3600MHz - 4000MHz) so your input multiplied by the feedback divider must be within this range. Using 50MHz input, enable the doubler (located in PLL CTRL (F2)). Next set the PLL2 N feedback divider to 40 (B counter set to 10 and A counter set to 0) to allow the VCO to lock to 4000MHz. Then set the VCO divider to 4 and the OUT2 divider to 5 to give you the desired 200MHz clock frequency.
Next you will want to configure the loop filter for the output PLL as follows (located on page 7 of the document):
- Pole2 Resistor = 225 ohms
- Zero Resistor = 2.75k ohms
- Pole 1 cap = 0pF
- PLL2 charge pump = 896uA
These settings should give you a loop bandwidth of 430kHz and ~75 degrees of phase margin. Please let me know if you have any questions.
Regards,
Kyle