I don't think the 21479 is up for this task.
The only interface on the 21479 that you can use for this is the PDAP (see Ch 12 in the HRM). I think your problem is going to be the transfer rate available to the internal FIFO. This happens at PCLK/4 which is also core clock / 8.
You would need a core clock of almost 500M which is not going to happen with the 21479.
The PulSAR ADC can be made to work although it is a little tricky. I have done this with SPORTs. The catch here is that you need to pay attention to the convert period and the data transfer. This will be somewhat clearer looking at the AD7985 timing diagram. The internal PCG in the SHARC works well for setting convert and data transfer clocks.
There is enough internal memory for your fifo.
You could consider a 21469 for this task. I think the link ports could manage the 65M ADC. You could implement the PulSAR ADC with a SPORT (and a small amount of glue logic). Of course, this does give up power consumption but might still be an alternative to an FPGA.
Al Clark
www.danvillesignal.com