I have been customizing the FMComms2 Zedboard reference design and recently discovered that Vivado is failing to meet timing constraints. After a lot of debugging I noticed that some of the timing constraints in the original reference design were missing from my design. I ran the "write_xdc master.xdc" tcl command to write the master set of constraints for the original and modified projects and compared the two files. What I found is that I was missing the creation of asynchronous clock groups. Here is are the constraints from the reference design which I was missing:
#################################################
# Constraints from file : 'axi_dmac_constr.tcl'
#################################################
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_system_wrapper/system_i/axi_ad9361_dac_dma/inst/s_axi_aclk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_system_wrapper/system_i/axi_ad9361_dac_dma/inst/m_src_axi_aclk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_system_wrapper/system_i/axi_ad9361_adc_dma/inst/s_axi_aclk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_system_wrapper/system_i/axi_ad9361_adc_dma/inst/m_dest_axi_aclk]]
I copied these lines into the constraints file for my custom project. Now that Vivado isn't trying to optimize the paths between these clock domains, the design meets timing.
So here is my question- why isn't the 'axi_dmac_constr.tcl' generating these constraints for my custom project? The master.xdc for my custom project has two instances of the "Constraints from file : 'axi_dmac_constr.tcl'" but there are no constraints below the headers. This tells me the tcl script is being run, it just isn't doing anything. Any help would be appreciated.