HI Ian,
We are interested in adding digital post‑linearization to increase the effective resolution of ADC. The goal is to suppress low order non‑linearities of the ADC. I've seen a few papers online discussing this, and there is a company named SP Devices that sells IP for this. I would like to implement an algorithm in the FPGA that follows the ADC.
The AD9625 appears to meeting the SFDR as specified in the data sheet, ~77 dBc. We really need 10 dB better.
Thank you,
David