Hi Kyle,
We got it working. Both PLLs are locked now.
0x233 was one of the issues - this part is quite configurable and we had a hard time figuring out how to enable power to all modules needed.
How should we chose the PLL1 loop filter bandwidth? I know it should be <1/10 of PFD frequency. If we don't care about locking time and just want to get the lowest jitter possible is 30Hz ok?
Or is it to low?
Valentin