Hello Edwin,
I have mis-understood of ADV7611 data output timing.
t11 of ADV7611 is descrivbed as
"End of valid data to negative clock edge"
and t12 is described as
" negative clock edge to start of valid data"
This means the valid data start from end of "t12".
And ADV7611 output data is indefinite at negative edge of LLC.
I attached picture which is the relation of clock and data timing between ADV7611 and ADV7125.
If this timing is true, ADV7125 hold time may not be guaranteed by ADV7611.
In worst case, -0.67ns will be short when CLOCK frequency is 165MHz.
Is this understanding true ?
Best regards,
ysuzuki
