Hello Jiulu.
It is probably best to instead compare the 0.6 silicon to the most recent silicon that you have working (0.4) rather than 0.2. Silicon fixes implemented across the chip from revision 0.2 to 0.3 to 0.4 would exonerate any design changes implemented to fix known anomalies (these could be fixes to PPI, DMA, cache, etc.). If we use 0.4 as the baseline for what was working for you, we can focus on changes between 0.4 and 0.6 to try to identify if anything might be related. To that, I have retrieved an older version of the anomaly list that includes 0.4 silicon (as the one on the web only describes 0.5 and 0.6) for you to reference.
In addition, if you could provide more details regarding the failure description of "dazzling" in terms of what it means from the data perspective, that would be helpful. Also, a full listing of the following registers will help to fully describe the mode you are using and how you have the processor configured:
All PPI registers
All PPI DMA registers
PLL_CTL
PLL_DIV
VR_CTL
And if you could provide the following details about the application, that would help complete the picture:
1> What is your CLKIN?
2> What is your VDDEXT set to?
4> If you are NOT using the on-chip regulator, what is your VDDINT set to?
-Joe