Hi Frankd,
The main thing to understand with this interface is that there is a quiet time where the interface cannot be clocked. This is the time where the internal registers could be updating with the new data values. This quiet time is effectively set by the times tMSB and tCLKL.
Following the conversion start (rising edge on CNV) - you can clock the converter until the tCLKL time has elapsed. The result on the bus will be the result from the previous conversion.
You can begin to clock the converter again when the tMSB time has elapsed. The time in between is the quiet time.
The slides illustrate this timing in a way that is easier to understand but both the slides and the datasheet are effectively showing the same thing.
The user has the choice on where they want to clock the converter as long as they avoid the quiet time.
Regards,
ClaireL