Hey Kyle...
On FMCOMMS1 we have 19.2MHz which generate 768MHz for Sys Clock. I did not changed this in the original clock generation drivers written by AD for 122.88MHz.
You are right about R and S... it is a little difference in the datasheet and the Excel file calculation... comparing the original registers for 122.88MHz I should calculate digital loop filter coeffs (alpha, beta, ...) by 30MHz*S/R and for S and R I should use 30MHz*(S+1)/(R+1)... am I right? I checked with an oscilloscope, I measure 80MHz with this number...
For instance, I set as below:
R: 125
S: 335
U: 0
V: 1
(The rest are calculated in the Excel file with R=126 and S=336)
alpha0: 0xE438
alpha1: 0x9
alpha2: 0
alpha3: 0
beta0: 0x13141
beta1: 0x10
gamma0: 0x147d8
gamma1: 0x10
delta0: 0x44cb
delta1: 0x0b
You may have another suggestion for R and S.
When I read AD9548_REG_DLL_STATUS_0 (0x0D0A) I have 0x62 shows Freq is lock bot Phase is not... I checked with original 122.88MHz I have the same result... Is is OK?