Additional observation:
I'm capturing data at the RX port and below in the image is happening. There's a random gap (but happening frequent enough to capture) and then the received signal is turning into garbage. this is explaining why the measured rssi is varying. However, I'm still trying to understand what is wrong with LTE 10 MHz configuration On TX path I didn't see any issues with the same clock and sampling rates. When I bypass the RX FIR and decrease the ADC clock to half (122.88 MHz) I don't see this problem happening. The data ports are configured as CMOS and wondering could this be a problem for the chip driving data with clock speed at 30.72 MHz (configuration is CMOS, dual port, DDR, 2RX2TX, FDD) Can you please confirm that this DATA_CLK and Rx sampling rate (15.36 MSPS) OK for the CMOS? And any ideas what else could be wrong?
Thank you,
Asli
