The DDR can not keep up- this is a system level issue that you can not solve with software (VDMA).
You need to modify the design to have the VDMA write to a buffer and let DAC read from this buffer.
You could modify the memory above to do the same - but note that this is NOT a circular buffer.
What you need is to collect the entire sample set inside the FPGA (from DDR or other sources).
