Thanks for the help so far.
We now seem to have access to all the registers, and can set the AD1938 up as we want, but have found another issue. We want the ADC to run directly from the local MCLKI/XI pin running (now) at 512xFs. The DAC should use the PLL locked to the incoming DLRCLK. Incidentally the ADC output is then sent to the DAC in another (identical) unit over fibre, which also sends back return audio over another fibre.
The DAC works fine with the PLL locked to the DLRCLK. It appears that the ADC also works fine from the MCLKI/XI input, until we disconnect the DLRCLK input to the DAC. There is then no output from the ADC. The PLL obviously loses lock, but it appears that this also stops the ADC working from MCLKI/XI. Why might this be?
I see a note in the description of PLL and Control Register 0 where you define the MCLKI/XI pin functionality (PLL active), master clock rate setting. What is the meaning of the 'PLL active'? Why is it mentioned? Does it mean that the MCLK/XI pin direct to the ADC does not function if the PLL is inactive or unlocked?
Thanks.
Andrews