Hello Jin,
I was able to replicate the problem on the bench. What has been the delay is that I am trying to find a workaround solution for you. The solution would only work if the system knows when the ADC clocks will be invalid. Unfortunately it appears that the PLL Unlock logic is always connected to the DAC mutes even if the DAC is not using the PLL. But, there may still be a workaround.
So does the system controller know in advance when the clocks will be invalid?
Thanks,
Dave T