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Re: PLL initialization example related to EE-357

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Hi Thomas,

 

1. Start the processor at 400MHz.

2. Read the SVS_DAT register and verify contents

3. Program the power supply to operate at the voltage indicated by the contents in the SVS_DAT register

4. Reprogram the PLL to operate at 450MHz, after doing all of the above.

 

Yes, you should follow the same steps to enable core clock speeds of up to 450 MHz. Please note that Static Voltage Scaling is only available on parts specifically designed for SVS operation. This includes certain ADSP-2148x SHARC processor variants. For more details on supported devices and corresponding power consumption

figures, please refer to the ADSP-2148x SHARC processor datasheet. Also, please refer to the Figure 3 given in the application note (EE-357) for the hardware reference to implement programmable regulator.

 

The crux of our questioning in this forum is related to exactly HOW to "Reprogram PLL in software to 450MHz" as described on page 7 of EE-357.

Are there any special considerations, or would we simply use code similar to that described in EE-290?

Once you program the Voltage regulator to new VDD_INT value, directly you can program the PLL in software to 450MHz. There is no any special considerations, and you can use code similar to that described in EE-290.


Regars,

Jithul


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