Thank you for providing the code example.
Your problem is related to the notes on page 13 of the user guide
Peripheral clock must be greater than or equal to the FCLK. FCLK is set by CLKCON0[2:0].
Calculations are for UCLK = 16 MHz with CLKSYSDIV[0] set to 0. An additional divide by 2 is required if CLKSYSDIV[0] is set to 1