Hi Ashwin,
I am using a customised board from other vendor.
I am following the example from H264_MP_Encoder_Developer_Guide_Rel3.0.0 and it appeared to fail more frequently at zero degree.
CORECLK 600MHz
SYSCLK 100MHz
I forget to mentioned that I attempted to do a soft core and system reset when the encoding fail. Would like to also check does the follow reset codes do a reset of program counter or will it re-read the program from flash again?
*************************************************************************************************
#include "defBF561.h"
////////////// C O D E ////////////////
.section drivers_L1_code;
.align 4;
dummy_start:
.global system_reset, systemreset ;
system_reset:
systemreset:
/* Issue system soft reset */
P0.L = LO(SICA_SWRST) ;
P0.H = HI(SICA_SWRST) ;
R0.L = 0x0007 ;
W[P0] = R0 ;
SSYNC ;
/* *******************
Wait for system reset to complete (needs to be 5 SCLKs). Assuming a worst case CCLK:SCLK ratio (15:1), use 5*15 = 75 as the loop count.
*/
P1 = 75 ;
LSETUP(start, end) LC0 = P1 ;
start:
end:
NOP ;
/* Clear system soft reset */
R0.L = 0x0000 ;
W[P0] = R0 ;
SSYNC ;
/* Core reset - forces reboot */
RAISE 1 ;
system_reset.END:
systemreset.END:
rts;
dummy_end:
*************************************************************************************************
Regards,
Eric