Sir,
thanks for the explaination.
The symbol timing recovery block implemented in simulink, it is not supported by the system generator.So no verilog code can be generated for it.So can that block be implemented in xilinx fpga?
or the symbol timing recovery block has to be implemented in matlab and the output of adc (ad9643 - pulse shaped and filtered Rx_I_out and RX_q_out) has to be given to matlab through some sort of communication medium(serial , hdmi ).
thanks
gitanjali