Hi,
Currently, i'm working on Zedboard, + FMCOMMS1.
I already successfully design and implementation of complex multiplier using Verilog HDL ( figure below). The synthesis , and implementation done using PlanAhead, XPS and running using SDK to test my application into Zedboard. it run perfectly. My project is to use this complex multiplier to perform modification on I,Q data before it send over to the air.
So I will control this IQ modification thru Real_B and Ima_B . Meanwhile the original IQ will feed thru Real_A and Ima_A.
Based on test.c , some code stated
| data_i = (sine_lut[index_i] << 16); | ||
| data_q = (sine_lut[index_q] << 0); | ||
| Xil_Out32(DDRDAC_BASEADDR + index * 4, data_i | data_q); |
so data_i will represent my Real_A and data_q will represent my Ima_B. Result form my complex multiplier has 64-bit. and this result suppose to send over to the air/ DDRDAC. Result from this complex multiplier can be read as per code below..
Result_Real=COMPLEX_MULTIPLIER_CORE_mReadSlaveReg4(XPAR_COMPLEX_MULTIPLIER_CORE_0_BASEADDR,0);
Result_Imag=COMPLEX_MULTIPLIER_CORE_mReadSlaveReg5(XPAR_COMPLEX_MULTIPLIER_CORE_0_BASEADDR,0);
Now , my question is
1- What is the best way to pass these data (Result_Real, Result_Imag) into DDRDAC_BASEADDR ? What should I do on this code " Xil_Out32(DDRDAC_BASEADDR + index * 4, data_i | data_q);"
2-Any concern on clk or frequency? DAC frequency around 500Mhz, but FPGA cannot reach that par. Should I use board frequency for custom logic only?
Best Regards,
Mohd Nazrin