Re: AD9548 - Autosync - sync on DPLL phase lock

Hi Neil,

Thanks for the detailed explanation.

I use currently the default settings for the phase-lock threshold set by the profile designer. I will try set a narrower window...

How I currently switch between the profiles:

1. Register 0x403 is always set to 0x02 - Sync on phase lock.
2. I wait until profile 0 (higher bandwidth) is frequency and phase locked. I see on the scope that this event synchronises the output dividers.
3. I clear the holdover history and wait for ~30s until a new average is accumulated as the OCXO is still drifting and the previous history would otherwise kick the PLL out of lock.
4. I switch the loop into holdover.
5. I assign the new profile 1 with the lower bandwidth.
6. I close the loop again and wait until frequency and phase is locked. This time the output divider is not synchronised which is correct.

I can see on the scope that the phase of the output signal is at this stage still drifting towards the reference pulse but in some cases either stops before or after the reference pulse, which causes then the +/-50ns phase offset.

You say I should try programming register 0x0403 = 0x01 (Sync on frequency lock) after I switch to profile 1 with the lower bandwidth which rises a few more questions:

1. Do you mean I should program 0x0403 = 0x01 or probably 0x02 because I want it actually phase locked?
2. Doing so, would that mean the output divider is then synchronised after profile 1 achieves frequency and phase lock?
3. What would be the best procedure tho switch between profiles?

Regards,

Fred