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Re: How can I use the SIMD +PEy feature

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Hello,

 

All the source codes are available in the CCES Installation path

“.\Analog Devices\CrossCore Embedded Studio 2.2.0\SHARC\lib\src\libdsp_src”

 

The library codes present here have a SIMD version for fir_decima, fir_interp, fir_vec , all optimized for SHARC+ Core architecture but the fir() function has a SISD implementation.

You can refer to the application note EE375 “Migrating Legacy SHARC to ADSP-SC58x/2158x SHARC+ Processors” to get the SIMD implementation of FIR function optimized for SHARC+ Core architecture

http://www.analog.com/media/en/technical-documentation/application-notes/EE375v01.pdf

 

Regards,

Mahesh


ADIS16000 connector

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Hi all,

 

I have a question regarding exact type of the connector on ADIS16000 for connection to microcontroller. I'm planning to build an arduino based data logger for ADIS1229 data.

Datasheet describes that we can use 'standard 1mm, 14 pin'  connector?

I would like to purchase a cable that can be attached to this connector with loose wires on the other side?

 

Alternatively, I can use ADIS16COM1 breakout board, but I cannot find PIN layout for ADIS16COM1 J1 connector in the documentation..

 

thanks,

 

Davor

AD5696R I2C SDA stuck on GND

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Hi.

I have a problem with the i2c Interface of the AD5696R.

I wrote a test procedure with the intention to test my read an write function for an EEPROM which shares the bus with two of these DACs and some other IC. This functions  sends multiple bytes starting with value 0x10 and increasing it by 1 with each byte.

For some strange reason the AD5696 responds to a bit-pattern that matches its address (one is configured ad 0x0E, the other 0x0F) in the middle of the transfer.

 

As result the master (an Atmel SAMA5D3) does release the clock line when it recognizes the "second master" that drives against it's data line. This Situation is shown on the screenshot. The test procedure sends the Bytes 0x1A, 0x1B, 0x1C and at last a 0x1D which matches the 0x0E address followed by 1 bit for a read transfer. I assume the DAC now sends it's ack which is transparent for the master as the regular adressed slave also sends an ack. Now the  DAC sends 3 additional zeros witch are also transparent because the master is sending the first 3 bits of 0x1D. In the moment the master releases the data line to send the first 1 it recognizes someone forced the line to zero and stops sending data

 

I'm not able to end the transfer by manually generating clock cycles. The AD5696 is freezed in its state. Only a reset can release the data line.

If I disconnect the DAC with adress 0x0E from the bus the same problem appears with a pattern matching the 0xF address of the second DAC.

 

Do you have any idea?

Re: ADSP-BF706 Security Backend

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Hi Bernhard,

 

As Gabby mentioned, for digital signature it uses ECDSA NIST 224 bit algorithm.

 

Yes this signature is calculated for an un-encrypted loader image. There are three image formats which can be generated from normal(unsigned and un-encrypted) loader stream:

  1. BLp: This is only a signed image and used for authentication of the image.
  2. BLx: This is both signed and encrypted image. This is used for both authentication and confidentiality.
  3. BLw: This is both signed and encrypted image. The key used for encrypting the image is also encrypted using a wrapper key. This is used for both authentication and confidentiality.

 

Whenever a normal loader stream is signed or authenticated, a secure boot stream comprises of the 180 bytes of secure header which holds information related to type of image present. This details of the header information is present in EE-366 and the hardware reference manual.

 

Please let us know if you have any further queries.

 

Thanks,

Harshit

Re: ADF5355 Phase Resync

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Dear support,

any comment on the previous request?

Thank you

Luca

Footprint for HMC476MP86/476MP86E ?

AD7734 Nominal Input Voltage Range

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Hi,

 

I was using AD7734 in 0 to +5v mode with CLAMP = 1. It was working nicely.

 

However, I changed the configuration to CLAMP = 0 and I get only 0000s when I send negative voltages. The sign bit behaves correctly, but the negative results are clamped. If I go above 5V, the results are not clamped. So the clamp bit is set correctly, but does not work for negative voltages?

ADG858 for USB?

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Hi,

 

Could you please confirm if I can use two channels of ADG858 for USB data lines? I checked the important specifications (like On resistance, on resistance flatness, matched on resistance, bandwidth) for this device and compared with some devices which are recommended by AD for USB applications, such as ADG787. It seems that the USB requirements are satisfied by ADG858 too. But there is nothing mentioned about USB in ADG858's data sheet. I didn't find an eye diagram in it either.

 

The reason that I prefer to use ADG858 is that I need its four matched channels and I will be using two of them for USB data lines. Could anyone tell me if I am going wrong about this?


Re: data flow of digital loop back

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Hi Michael:

     I have seen the webpage before, and my confusion is also come from the webpage. In the webpage, there are some sentences below:

The next step is to tune the transmit path. Since AD9361 has no such monitors in the transmit path, it is set to be in digital loopback mode. Individual (separate equations) PRBS patterns are sent from the FPGA in the transmit path and are monitored in the receive path.

 

I am just curious that how the PRBS patterns in AD9361's transmit path are transferred to AD9361's receive path in digital loop back mode?

 

thanks

Gan

    

Re: Footprint for HMC476MP86/476MP86E ?

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Hi Syed,

 

Note that HMC476MP86`s status is Last Time Buy.

We do not have altium libraries, butattached zip file contains the manufacturing files of the EVB, that you can use to generate the footprint library for altium.

 

For samples, please contact with your local ADI sales contact, details can be found on ADI webpage.

 

Best,

Kagan

Re: Need help on energy based selector/mixer

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Hi Bob,

 

I was working on the schematic an noticed that the output of the multipliers are not a real rectified signal.

Neither is the output of the absolute value block. At least if you output the signal directly and view it on a

scope. It is an inverted and offset rectified signal.

ADS00016.BMP

I tried to invert the signal and use a clipper to cut off the bottom half. But the clipper does not seem to do it's

job. Most of the time the top clipper clips the bottom and vice versa. In the picture below the clipper is set to

Top: 0 Bottom: -0.9

ADS00024.BMP

 

After some testing, it seems that the DSP has problems outputting DC signals.

Re: HMC6000/6001 Alternative parts

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Hello,

 

The HMC6000/6001 will be replaced by the HMC6300/6301.  The new devices will not be available as bare die, the die are enclosed in an eWLB 4x6mm package, this greatly simplifies the assembly process.  There is also a significant increase in the performance using the HMC6300/6301.  Expected release is end of May 2016.

 

Regards,

Mark

Re: I want to make limb lead circuit by AD8232

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Hi Kevin,

 

I'm not aware of any reference designs or circuits using the AD8232 which discuss the application you are talking about.  I've forwarded this question to a colleague to see if he knows any more information for you, and he'll get back to you on this forum.

 

In the mean time, we do have other designs in the ECG reference designs using other products.  So you could take a look at those and see if you they help your application www.analog.com/cn0308

 

Cheers,

Brandon

Re: IQ correction in FPGA

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Hi Lars:

     If there is IQ correction in FPGA, is the IQ correction in AD9361 chip needed?

thanks

Gan

Re: HMC6000/6001 Alternative parts

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Hello Mark D'Amato.

Thank you for your answer. There is a additional question. Is HMC6300/6301's evaluation board expected release end of May 2016 too?


Re: ADV7619 - 8-5 TMDS Minimum Differential Swing Tolerance

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Hi,

your question has been forwarded to the part specialist

Best Regards,

Jeyasudha.M

Re: ADUM4160BRIZ / 60601-1 ed3.1

Re: FMCOMMS2 - reset cpack when DMAC dest is disabled?

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Do you have a suggestion for using the DMAC with packetized data?

 

What I would like to do for example is to send an FFT of the IQ through the RX DMAC, and (assuming FFT output is natural order) have the first result in the DMA always be bin0. My data flow is

     One channel IQ (32 bits) ---> FFT (32 bits out) ---> DMAC (32 to 64) ----> Zynq HP port

The FFT is held in reset when fifo_wr_xfer_req is low. But still the first sample is not always bin0.

uCOS licensing question

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I was hoping somebody out there has experience with licensing uCOS for CCES. We recently purchased license for uCOS. All of the on-line docs suggested that this was a "per product" license. When we received the key however it could only be installed on one developers PC.

Re: FMCOMMS2 - reset cpack when DMAC dest is disabled?

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Hi,

 

Do you use the FIFO interface or streaming AXI between the DMAC and the FFT?

 

- Lars

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